Page "Application-specific integrated circuit" Paragraph 27

This is effectively the same definition as a gate array.

What makes a structured ASIC different is that in a gate array, the predefined metal layers serve to make manufacturing turnaround faster.

In a structured ASIC, the use of predefined metallization is primarily to reduce cost of the mask sets as well as making the design cycle time significantly shorter.

For example, in a cell-based or gate-array design the user must often design power, clock, and test structures themselves ; these are predefined in most structured ASICs and therefore can save time and expense for the designer compared to gate-array.

Likewise, the design tools used for structured ASIC can be substantially lower cost and easier ( faster ) to use than cell-based tools, because they do not have to perform all the functions that cell-based tools do.

In some cases, the structured ASIC vendor requires that customized tools for their device ( e. g., custom physical synthesis ) be used, also allowing for the design to be brought into manufacturing more quickly.