Page "Athlon" Paragraph 16

One limitation ( also afflicting the Intel Pentium III ) is that SRAM cache designs at the time were incapable of keeping up with the Athlon's clock scalability, due both to manufacturing limitations of the cache chips and the difficulty of routing electrical connections to the cache chips themselves.

It became increasingly difficult to reliably run an external processor cache to match the processor speeds being released-and in fact it became impossible.

Thus initially the Level 2 cache ran at half of the CPU clock speed up to 700 MHz ( 350 MHz cache ).

Faster Slot-A processors had to compromise further and run at 2 / 5 ( up to 850 MHz, 340 MHz cache ) or 1 / 3 ( up to 1 GHz, 333 MHz cache ).

This later race to 1Ghz ( 1000 MHz ) by AMD and Intel further exacerbated this bottleneck as ever higher speed processors demonstrated decreasing gains in overall performance-stagnant SDRAM cache memory speeds choked further improvements in overall speed.

This directly lead to the development of integrating L2 cache onto the processor itself and remove the dependence on external cache chips.

AMD's integration of the cache onto the Athlon processor itself would later result in the Athlon Thunderbird.