Page "Complex instruction set computing" Paragraph 7

The circuitry that performs the actions defined by the microcode in many ( but not all ) CISC processors is, in itself, a processor which in many ways is reminiscent in structure to very early CPU designs.

In the early 1970s, this gave rise to ideas to return to simpler processor designs in order to make it more feasible to cope without ( then relatively large and expensive ) ROM tables and / or PLA structures for sequencing and / or decoding.

The first ( retroactively ) RISC-labeled processor ( IBM 801-IBMs Watson Research Center, mid-1970s ) was a tightly pipelined simple machine originally intended to be used as an internal microcode kernel, or engine, in CISC designs, but also became the processor that introduced the RISC idea to a somewhat larger public.

Simplicity and regularity also in the visible instruction set would make it easier to implement overlapping processor stages ( pipelining ) at the machine code level ( i. e. the level seen by compilers.

) However, pipelining at that level was already used in some high performance CISC " supercomputers " in order to reduce the instruction cycle time ( despite the complications of implementing within the limited component count and wiring complexity feasible at the time ).

Internal microcode execution in CISC processors, on the other hand, could be more or less pipelined depending on the particular design, and therefore more or less akin to the basic structure of RISC processors.