Page "Hardware description language" Paragraph 33

A HDL is analogous to a software programming language, but with major differences.

Many programming languages are inherently procedural ( single-threaded ), with limited syntactical and semantic support to handle concurrency.

HDLs, on the other hand, resemble concurrent programming languages in their ability to model multiple parallel processes ( such as flipflops, adders, etc.

) that automatically execute independently of one another.

Any change to the process's input automatically triggers an update in the simulator's process stack.

Both programming languages and HDLs are processed by a compiler ( usually called a synthesizer in the HDL case ), but with different goals.

For HDLs, ' compiler ' refers to synthesis, a process of transforming the HDL code listing into a physically realizable gate netlist.

The netlist output can take any of many forms: a " simulation " netlist with gate-delay information, a " handoff " netlist for post-synthesis place and route, or a generic industry-standard EDIF format ( for subsequent conversion to a JEDEC-format file ).