Page "Instruction-level parallelism" Paragraph 20

In recent years, ILP techniques have been used to provide performance improvements in spite of the growing disparity between processor operating frequencies and memory access times ( early ILP designs such as the IBM 360 used ILP techniques to overcome the limitations imposed by a relatively small register file ).

Presently, a cache miss penalty to main memory costs several hundreds of CPU cycles.

While in principle it is possible to use ILP to tolerate even such memory latencies the associated resource and power dissipation costs are disproportionate.

Moreover, the complexity and often the latency of the underlying hardware structures results in reduced operating frequency further reducing any benefits.

Hence, the aforementioned techniques prove inadequate to keep the CPU from stalling for the off-chip data.

Instead, the industry is heading towards exploiting higher levels of parallelism that can be exploited through techniques such as multiprocessing and multithreading.