Page "PA-RISC" Paragraph 8

An interesting aspect of the PA-RISC line is that most of its generations have no Level 2 cache.

Instead large Level 1 caches are used, formerly as separate chips connected by a bus, and now integrated on-chip.

Only the PA-7100LC and PA-7300LC had L2 caches.

Another innovation of the PA-RISC was the addition of vectorized instructions ( SIMD ) in the form of MAX, which were first introduced on the PA-7100LC.