Page "POWER1" Paragraph 7

The POWER1 is a big-endian CPU that uses a Harvard style cache hierarchy with separate instruction and data caches.

The instruction cache, referred to as the " I-cache " by IBM, is 8 KB in size and is two-way set associative with a line size of 64 bytes.

The I-cache is located on the ICU chip.

The data cache, referred to as the " D-cache " by IBM, is 32 KB in size for RIOS. 9 configurations and 64 KB in size for RIOS-1 configurations.

The D-cache is four-way set associative with a line size of 128 bytes.

The D-cache employs a store-back scheme, where data that is to be stored is written to the cache instead of the memory in order to reduce the number of writes destined for the memory.

The store-back scheme is used to prevent the CPU from monopolizing access to the memory.