Page "Race condition" Paragraph 0
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Here, ∆ t < sub > 1 </ sub > and ∆ t < sub > 2 </ sub > represent the propagation delay s of the logic elements.
When the input value ( A ) changes, the circuit outputs a short spike of duration (∆ t < sub > 1 </ sub >+∆ t < sub > 2 </ sub >)-∆ t < sub > 2 </ sub > = ∆ t < sub > 1 </ sub >.
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1.925 seconds.