Page "Static random-access memory" Paragraph 15

Assume that the content of the memory is a 1, stored at Q.

The read cycle is started by precharging both the bit lines to a logical 1, then asserting the word line WL, enabling both the access transistors.

The second step occurs when the values stored in Q and < span style =" text-decoration: overline ;"> Q </ span > are transferred to the bit lines by leaving BL at its precharged value and discharging < span style =" text-decoration: overline ;"> BL </ span > through M < sub > 1 </ sub > and M < sub > 5 </ sub > to a logical 0 ( i. e. eventually discharging through the transistor M < sub > 1 </ sub > as it is turned on because the Q is logically set to 1 ).

On the BL side, the transistors M < sub > 4 </ sub > and M < sub > 6 </ sub > pull the bit line toward V < sub > DD </ sub >, a logical 1 ( i. e. eventually being charged by the transistor M < sub > 4 </ sub > as it is turned on because < span style =" text-decoration: overline ;"> Q </ span > is logically set to 0 ).

If the content of the memory was a 0, the opposite would happen and < span style =" text-decoration: overline ;"> BL </ span > would be pulled toward 1 and BL toward 0.

Then these BL and < span style =" text-decoration: overline ;"> BL </ span > will have a small difference of delta between them and then these lines reach a sense amplifier, which will sense which line has higher voltage and thus will tell whether there was 1 stored or 0.

The higher the sensitivity of sense amplifier, the faster the speed of read operation is.