Help


from Wikipedia
« »  
During read accesses, the bit lines are actively driven high and low by the inverters in the SRAM cell.
This improves SRAM bandwidth compared to DRAMs — in a DRAM, the bit line is connected to storage capacitors and charge sharing causes the bitline to swing upwards or downwards.
The symmetric structure of SRAMs also allows for differential signaling, which makes small voltage swings more easily detectable.
Another difference with DRAM that contributes to making SRAM faster is that commercial chips accept all address bits at a time.
By comparison, commodity DRAMs have the address multiplexed in two halves, i. e. higher bits followed by lower bits, over the same package pins in order to keep their size and cost down.

2.035 seconds.