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The SA-110 contained 2. 5 million transistors and is 7. 8 mm by 6. 4 mm large ( 49. 92 mm < sup > 2 </ sup >).
It was fabricated by DEC in its proprietary CMOS-6 process at its Fab 6 fab in Hudson, Massachusetts.
CMOS-6 was DEC's sixth-generation complementary metal – oxide – semiconductor ( CMOS ) process.
CMOS-6 has a 0. 35 µm feature size, a 0. 25 µm effective channel length but for use with the SA-110, only three levels of aluminium interconnect.
It used a power supply with a variable voltage of 1. 2 to 2. 2 volts ( V ) to enable designs to find a balance between power consumption and performance ( higher voltages enable higher clock rates ).
The SA-110 was packaged in a 144-pin thin quad flat pack ( TQFP ).

1.799 seconds.