Page "Unicore" Paragraph 5

The instructions are almost identical to the standard ARM formats, except that conditional execution has been removed, and the bits reassigned to expand all the register specifiers to 5 bits.

Likewise, the immediate format is 9 bits rotated by a 5-bit amount ( rather than 8 bit rotated by 4 ), the load / store offset sizes are 14 bits for byte / word and 10 bits for signed byte or half-word.

Conditional moves are provided by encoding the condition in the ( unused by ARM ) second source register field Rn for MOV and MVN instructions.