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*** Parallel processing of CPU and a single multiply or a divide instruction
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*** and Parallel
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*** and CPU
*** and single
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*** and multiply
*** Hardware 16-bit × 16-bit → 32-bit multiply with optional accumulation ; 32-bit ÷ 16-bit → 16-bit divide
*** and instruction
*** Else, if the instruction is a store then: wait for the value to be stored before sending it to the memory unit
*** Entry to the Shift_IR stable state goes via the Capture_IR state, loading the shift register with a partially fixed value ( not the current instruction )
4.504 seconds.