** 8-bit CPU, 16-bit address space

** Commodore 64 ( or C64 or C = 64 ), an 8-bit home computer released by Commodore International in August 1982, the single best-selling personal computer model of all-time

** Commodore 128 ( or C128, CBM 128, or C = 128 ), a home / personal computer introduced in January 1985, the last 8-bit machine commercially released by Commodore Business Machines

** Commodore VIC-20, an 8-bit home computer announced in 1980

** Indexed register indirect with 8-bit signed offset e. g. 8 ( A0, D0 ) or 8 ( A0, A1 )

** Relative with 8-bit signed offset with index, e. g. 8 ( PC, D2 )

** Intel 8048 8-bit microcontroller running at 1. 79 MHz

** 8-bit data bus

** 8-bit single channel ( no DMA ), 16 kHz max using BIOS routines.

** Single precision – 36 bits: 1 sign bit, 8-bit characteristic, 27-bit mantissa

** 8-bit audio resolution

** 8-bit data bus

** Atari POKEY, used in Atari 8-bit computers, Atari 5200, and certain Atari 7800 cartridges.

** Modern 8-bit and 16-bit Microcontroller chips, such as Atmel AVR and TI MSP430 chips, support JTAG programming and debugging.

** Atari 8-bit

** In Atari 8-bit computers, three of the pins are used to read state of the console keys ( Start / Select / Option ).

** NCR 5380 " SCSI Controller " — 8-bit asynchronous transfers up to 4 MB / s.

** MOS Technology 8500 ( the 6510 / 8500 being a modified 6502 with an integrated 8-bit I / O port )

** Permanent memory ( ROM )- The instructions for in-built functions ( arithmetic operations, square roots, percentages, trigonometry etc.

** Arithmetic logic unit ( ALU )-The ALU executes all arithmetic and logic instructions, and provides the results in binary coded form.

** Superscalar architecture — The Pentium has two datapaths ( pipelines ) that allow it to complete two instructions per clock cycle in many cases.

** The microcode can employ both pipelines to enable auto-repeating instructions such as rep movsw perform one iteration every clock cycle, while the 80486 needed three clocks per iteration ( and the earliest x86-chips significantly more than the 486 ).

** A faster, fully hardware-based multiplier makes instructions such as MUL and IMUL several times as fast ( and more predictable ) than in the 80486 ; the execution time is reduced from 13 ~ 42 clock cycles down to 10 ~ 11 for 32-bit operands.

** branch to another location in the program and execute instructions there

** RISC — Requiring explicit memory loads, the instructions would be: load a, reg1 ; load b, reg2 ; add reg1, reg2 ; store reg2, c

** RISC — arithmetic instructions use registers only, so explicit 2-operand load / store instructions are needed: load a, reg1 ; load b, reg2 ; add reg1 + reg2 -> reg3 ; store reg3, c ; unlike 2-operand or 1-operand, this leaves all three values a, b, and c in registers available for further reuse.

** Specific instructions like rotations or three-operand addition aren't in some SIMD instruction sets.

** Advance health care directive ( living will ), instructions for medical decisions after one becomes incapacitated

** Ted Hoff and Stan Mazor and Larry Potter ( IBM Chief Scientist of IBM ) proposed a single-chip implementation of the CTC architecture, using RAM register memory rather than shift register memory, and also added a few instructions and interrupt facility.

** Extended instruction set ( Multiply instructions and instructions for handling larger program memories )

** R800 running at 7. 16 MHz ( instructions use about 4x less clock ticks than the Z80, so often quoted as 28. 6 MHz when comparing with the Z80 )

** 150 burial instructions carved on rock tombs.

** It is easier to predict the exact timing of a given sequence of instructions.

** Superscalar, three instructions per clock cycle

** Conditional random fields ( CRF ) are commonly used in conjunction with IE for tasks as varied as extracting information from research papers to extracting navigation instructions.

** Encoding of machine language instruction sets in which different instructions occupy different numbers of machine words and the start of an instruction is determined by the length of the preceding one

** The London e-Science Center has created a " Transfer-queue over Globus ( TOG )" package and provides instructions on how to configure a Globus Toolkit 2 or 3 or a Globus Toolkit 4 server so that it can submit jobs for execution on a local Sun Grid Engine installation.

** Radio data terminals: these are hand held or truck mounted terminals which connect by wireless to logistics automation software and provide instructions to operators moving throughout the warehouse.

** Branch table, a term used to describe an efficient method of transferring program control ( branching ) to another part of a program using a table of branch instructions.

** Article 11: Hungary should pay for the Allied Control Commission and that " The Government of Hungary will also assure, in case of need, the use and regulation of the work of industrial and transport enterprises, means of communication, power stations, enterprises and installations of public utility, stores of fuel and other material, in accordance with instructions issued during the armistice by the Allied ( Soviet ) High Command or the Allied Control Commission.

The 8051 microcontroller has two, a primary accumulator and a secondary accumulator, where the second is used by instructions only when multiplying ( MUL AB ) or dividing ( DIV AB ); the former splits the 16-bit result between the two 8-bit accumulators, whereas the latter stores the quotient on the primary accumulator A and the remainder in the secondary accumulator B.

As with many other 8-bit processors, all instructions were encoded in a single byte ( including register-numbers, but excluding immediate data ), for simplicity.

Most instructions have dot-letter suffixes, permitting operations to occur on 8-bit bytes (". b "), 16-bit words (". w "), and 32-bit longs (". l ").

In addition, there is an 8 x 8-bit multiply ( A x B ), with full 16-bit result, and Fractional / Integer 16-bit by 16-bit Divide instructions.

For the most early 8-bit and 16-bit microprocessors the performance was recognized in thousand instructions per second ( kIPS ), which equals 0. 001 MIPS.

Where a Harvard architecture is used, instruction words for the processor may be a different bit size than the length of internal memory and registers ; for example: 12-bit instructions used with 8-bit data registers.

The new instructions work on new data types: 64-bit packed vectors of either eight 8-bit integers, four 16-bit integers, two 32-bit integers, or one 64-bit integer.

The separate storage means the program and data memories can have different bit widths, for example using 16-bit wide instructions and 8-bit wide data.

CDC used the term " byte " to refer to 12-bit entities used by peripheral processors ; characters were 6-bit, and central processor instructions were either 15 bits, or 30 bits with a signed 18-bit address field, the latter allowing for a directly addressable memory space of 128K words of central memory ( converted to modern terms, with 8-bit bytes, this is 0. 94 MB ).

The transputer instruction set comprised 8-bit instructions divided into opcode and operand nibbles.

As in many other 8-bit processors, all instructions are encoded in a single byte ( including register-numbers, but excluding immediate data ), for simplicity.

* 4001: 256-byte ROM ( 256 8-bit program instructions ), and one built-in 4-bit I / O port.

Intel i860 instructions acted on data sizes from 8-bit through 128-bit.

Two instructions were stored in every word in 20-bit subwords consisting of an 8-bit instruction and a 12-bit address, the instructions being operated in series with the left subword running first.

* Most instructions are single cycle execution ( 2 clock cycles, or 4 clock cycles in 8-bit models ), with one delay cycle on branches and skips

It met IBM's main criteria: it looked like CP / M, and it was easy to adapt existing 8-bit CP / M programs to run under it, notably thanks to the TRANS command which would translate source files from 8080 to 8086 machine instructions.

These 16-bit CPUs were an evolution of the previous generation of 8-bit CPUs such as the 8080, inheriting many characteristics and instructions, extended for the 16-bit era.

This is an 8-bit enhanced Mid Range core with 14 additional instructions and optimizations for the C Programming Language.

The SPC700 instruction set is quite similar to that of the 6502 CPU family, but includes additional instructions, including XCN ( eXChange Nibble ) which swaps the upper and lower 4-bit portions of the 8-bit accumulator, and an 8-by-8-to-16-bit multiply instruction.

* The B6500 had variable length instructions with an 8-bit syllable instead of fixed length instructions with a 12-bit syllable.

The register set consisted of sixteen 16-bit registers, and there were instructions that could use them as 8-bit, 16-bit, 32-bit, and 64-bit registers.

The first commercial microprocessor was the binary coded decimal ( BCD-based ) Intel 4004, developed for calculator applications in 1971 ; it had a 4-bit word length, but had 8-bit instructions and 12-bit addresses.