(€ 19 million as a group ) However, in 2008 – 09 season saw the decrease of gate and TV income, co-currently with finished 6th in Serie A, which saw Roma made a net loss of € 1, 894, 330.

(€ 1. 56 million as a group ) The gate and TV income further slipped in 2009 – 10 season, made a net loss of € 21, 917, 292 ( already boosted by the sale of Alberto Aquilani ; € 22 million as a group ) despite sporting success ( the second in 2009 – 10 Serie A ).

* 1821 – Patriarch Gregory V of Constantinople is hanged by the Ottoman government from the main gate of the Patriarchate and his body is thrown into the Bosphorus.

His standing is underlined by his authoritativeness during the legal proceedings at the town gate ( 4: 1 – 10 ).

Their average home gate for the 2011 – 12 season was 41, 478, the sixth highest in the Premier League.

* 1905 – Former Idaho Governor Frank Steunenberg is assassinated at the front gate of his home in Caldwell.

* The MOSFET ( Metal – Oxide – Semiconductor Field-Effect Transistor ) utilizes an insulator ( typically SiO < sub > 2 </ sub >) between the gate and the body.

The Foreign Legion's First Battalion ( Lieutenant-Colonel Donnier ) was sent to Tonkin in the autumn of 1883, during the period of undeclared hostilities that preceded the Sino – French War ( August 1884 to April 1885 ), and formed part of the attack column that stormed the western gate of Son Tay on 16 December.

An example is the Phase – gate model.

Assyrian lammasu gate guardian from Khorsabad, c. 721 – 705 BCE

Panoramic view showing the northern city gate with fortifications. Copperplate by Frans Hogenberg around 1570 – 80.

The IGFET is more commonly known as a metal – oxide – semiconductor FET ( MOSFET ), reflecting its original construction from layers of metal ( the gate ), oxide ( the insulation ), and semiconductor.

Nevertheless, there are ways to use them, especially JFETs, as light-sensitive devices, by exploiting the photocurrents in channel – gate or channel – body junctions.

* February 8 – 20 fans of Olympiacos and 1 fan of AEK Athens die, while 54 are injured, after a stampede at the Karaiskakis Stadium in Piraeus, possibly because gate 7 does not open immediately after the end of the game.

* April 10 – Ecumenical Patriarch Patriarch Gregory V of Constantinople is blamed by the Ottoman government for being unable to suppress Greek independence and is hung outside the main gate of the Patriarchal Cathedral immediately after the celebration of Easter.

Variations of and successors to the basic TTL family, which has a typical gate propagation delay of 10ns and a power dissipation of 10 mW per gate, for a power – delay product ( PDP ) or switching energy of about 100 pJ, include:

The phrase " metal – oxide – semiconductor " is a reference to the physical structure of certain field-effect transistors, having a metal gate electrode placed on top of an oxide insulator, which in turn is on top of a semiconductor material.

: These are actually a JFET with the gate shorted to the source, and function like a two-terminal current-limiter analog to the Zener diode, which is limiting voltage.

The conductivity of the channel is a function of potential applied across the gate and source terminals.

All FETs have source, drain, and gate terminals that correspond roughly to the emitter, collector, and base of BJTs.

The size of the gate, length L in the diagram, is the distance between source and drain.

This gate permits electrons to flow through or blocks their passage by creating or eliminating a channel between the source and drain.

The body simply refers to the bulk of the semiconductor in which the gate, source and drain lie.

The FET controls the flow of electrons ( or electron holes ) from the source to drain by affecting the size and shape of a " conductive channel " created and influenced by voltage ( or lack of voltage ) applied across the gate and source terminals.

Further gate-to-source voltage increase will attract even more electrons towards the gate which are able to create a conductive channel from source to drain ; this process is called inversion.

For either enhancement-or depletion-mode devices, at drain-to-source voltages much less than gate-to-source voltages, changing the gate voltage will alter the channel resistance, and drain current will be proportional to drain voltage ( referenced to source voltage ).

Top = source, bottom = drain, left = gate, right = bulk.

Front-end surface engineering is followed by: growth of the gate dielectric, traditionally silicon dioxide ( SiO < sub > 2 </ sub >), patterning of the gate, patterning of the source and drain regions, and subsequent implantation or diffusion of dopants to obtain the desired complementary electrical properties.

For a field-effect transistor, the terminals are labeled gate, source, and drain, and a voltage at the gate can control a current between source and drain.

The four terminals of the FET are named source, gate, drain, and body ( substrate ).

The conductivity is varied by the electric field that is produced when a voltage is applied between the gate and source terminals ; hence the current flowing between the drain and source is controlled by the voltage applied between the gate and source.

The positive voltage attracts free-floating electrons within the body towards the gate, forming a conductive channel.

But first, enough electrons must be attracted near the gate to counter the dopant ions added to the body of the FET ; this forms a region free of mobile carriers called a depletion region, and the phenomenon is referred to as the threshold voltage of the FET.

In a p-channel depletion-mode device, a positive voltage from gate to body creates a depletion layer by forcing the positively charged holes away from the gate-insulator / semiconductor interface, leaving exposed a carrier-free region of immobile, negatively charged acceptor ions.

The semiconductor logic gate, on the other hand, acts as a high-gain voltage amplifier, which sinks a tiny current at its input and produces a low-impedance voltage at its output.

However, sodium is considered an extremely undesirable contaminant in MOSFET fabrication because it degrades the insulating properties of gate oxides ( specifically, sodium ions can migrate in and out of the gate, changing the threshold voltage of the transistor and making it harder or easier to turn the transistor on over time ).

For either mode, a more positive gate voltage corresponds to a higher current for N-channel devices and a lower current for P-channel devices.

The tunneling current is controlled by a voltage applied to the gate through a capacitor.

Note that the threshold voltage for this device lies around 0. 45 V. Nanowire MOSFETs lie towards the end of the ITRS roadmap for scaling devices below 10 nm gate lengths.

A cross section through an nMOSFET when the gate voltage V < sub > GS </ sub > is below the threshold for making a conductive channel ; there is little or no conduction between the terminals source and drain ; the switch is off.

In some cases ( e. g., when the output of a TTL logic gate needs to be used for driving the input of a CMOS gate ), the voltage level of the " totem-pole " output stage at output logical " 1 " can be increased up to V < sub > CC </ sub > by connecting an external resistor between the V < sub > 3 </ sub > collector and the positive rail.

NAND flash also uses floating-gate transistors, but they are connected in a way that resembles a NAND gate: several transistors are connected in series, and only if all word lines are pulled high ( above the transistors ' V < sub > T </ sub >) is the bit line pulled low.

As well as the Thames Barrier, the smaller gates along the Thames Tideway include Barking Barrier, King George V Lock gate, Dartford Barrier and gates at Tilbury Docks and Canvey Island must also be closed.

For example, although raising V < sub > m </ sub > opens most gates in the voltage-sensitive sodium channel, it also closes the channel's " inactivation gate ", albeit more slowly.

Other differences are with plugs that match 1 / 4-inch or 6. 3mm jacks, 3. 5mm jacks, and banana jacks, with main DC power supply ( typically ± 15 V, but ranging from ± 18 V to ± 12 V for different manufacturers or systems ), with trigger or gate voltages ( Moog S-trigger or positive gate ), with typical audio signal levels ( often ± 5 V with ± 5 V headroom ), and with control voltages of volts / octave ( typically 1 V / octave, but in some cases 1. 2 V / octave.