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MIPS and V
Multiple revisions of the MIPS instruction set exist, including MIPS I, MIPS II, MIPS III, MIPS IV, MIPS V, MIPS32, and MIPS64.
In 1999 MIPS formalized their licensing system around two basic designs, the 32-bit MIPS32 ( based on MIPS II with some additional features from MIPS III, MIPS IV, and MIPS V ) and the 64-bit MIPS64 ( based on MIPS V ).
Operating systems ported to the architecture include SGI's IRIX, Microsoft's Windows NT ( until v4. 0 ), Windows CE, Linux, BSD, UNIX System V, SINIX, QNX, and MIPS Computer Systems ' own RISC / os.
MIPS V was designed to improve the performance of 3D graphics applications.
MIPS V was complemented by the integer-only MIPS Digital Media Extensions ( MDMX ) multimedia extensions, which were announced on the same date as MIPS V.

MIPS and is
The processor is capable of speeds of up to 16. 58 MHz and can run up to 2. 7 MIPS ( million instructions per second ), for the base 68328 and DragonBall EZ ( MC68EZ328 ) model.
Another common representation of the Dhrystone benchmark is the DMIPS ( Dhrystone MIPS ) obtained when the Dhrystone score is divided by 1757 ( the number of Dhrystones per second obtained on the VAX 11 / 780, nominally a 1 MIPS machine ).
IRIX is a computer operating system developed by Silicon Graphics, Inc. ( SGI ) to run natively on their MIPS architecture workstations and servers.
Meanwhile, the mov reg, reg and ALU reg, reg instructions taking two and three cycles respectively yielded an absolute peak performance of between 1 / 3 and 1 / 2 MIPS per MHz, that is, somewhere in the range 3 – 5 MIPS at 10 MHz.
MIPS ( originally an acronym for Microprocessor without Interlocked Pipeline Stages ) is a reduced instruction set computer ( RISC ) instruction set architecture ( ISA ) developed by MIPS Technologies ( formerly MIPS Computer Systems, Inc .).
Several optional extensions are also available, including MIPS-3D which is a simple set of floating-point SIMD instructions dedicated to common 3D tasks, MDMX ( MaDMaX ) which is a more extensive integer SIMD instruction set using the 64-bit floating-point registers, MIPS16e which adds compression to the instruction stream to make programs take up less room, and MIPS MT, which adds multithreading capability.
Since the MIPS architecture is licensable, it has attracted several processor start-up companies over the years.
The Ingenic JZ4730 is an example for a MIPS based System on Chip | SoC
The low power-consumption and heat characteristics of embedded MIPS implementations, the wide availability of embedded development tools, and knowledge about the architecture means use of MIPS microprocessors in embedded roles is likely to remain common.
One of the more interesting applications of the MIPS architecture is its use in massive processor count supercomputers.
MIPS IV is the fourth version of the architecture.
It is a superset of MIPS III and is compatible with all existing versions of MIPS.
Modern mainframe design is generally less defined by single-task computational speed ( typically defined as MIPS rate or FLOPS in the case of floating point calculations ), and more by:

MIPS and version
The success of this initial processor version was limited to replacing PA-RISC in HP systems, Alpha in Compaq systems and MIPS in SGI systems, though IBM also delivered a supercomputer based on this processor.
Based on the MIPS R10000 processor, it scaled from 2 to 128 processors and a smaller version, the Origin 200 ( SN-00 ), scaled from 1 to 4.
The OOO version added support for Linux x86-64, Linux MIPS, Linux S390, Mac OS X x86 / PPC above 10. 4.
OOO version added support of Linux x86-64, Linux MIPS, Linux S390, Mac OS X x86 / PPC above 10. 4.
* Be based on an ARM version 4 compatible CPU, Intel XScale CPU, MIPS CPU or SH3 CPU.
In the early 1990s, a wave of UNIX workstation vendors — Sony, Motorola, Data General, MIPS, and Apollo — provided funding to Frame Technology for an OEM version for their platforms.
OSF / 1 had previously shipped in a version for the MIPS architecture in 1991, but was not considered or advertised as a mature product.
The current version of Windows Embedded Compact supports Intel x86 and compatibles, MIPS, and ARM processors.
Even on similar systems, the details of implementing a compatibility layer can be quite intricate and troublesome ; a good example is the IRIX binary compatibility layer in the MIPS architecture version of NetBSD.
This was followed in short order by SCO announcing that they were suspending all work on moving their version of Unix to the MIPS platform.
The later Magnums, the MIPS Magnum R4000PC and MIPS Magnum R4000SC, also used a MIPS microprocessor — the MIPS R4000, a full 64-bit microprocessor available either in a low-cost version ( the R4000PC ) having 16 kB of L1 cache but no L2 cache, or a higher-performance version ( the R4000SC ) with 1 MB of secondary cache in addition to the 16 kB of primary cache.
The MIPS Magnum R4000 ran either Windows NT ( beginning with version 3. 1 ) when equipped with the little-endian ARC firmware, or RISC / os when MIPS Computer Systems, Inc .' s proprietary big-endian firmware ( the " MIPS Monitor ") was installed.
The MIPS Magnum R4000 was supported by Windows NT from version 3. 1 ( released in 1993 ) through version 4. 0 ( released in 1996 ).

MIPS and architecture
* MIPS architecture, a RISC instruction set architecture
* MIPS Technologies, formerly MIPS Computer Systems, developer of the MIPS architecture
# REDIRECT MIPS architecture
Computer architecture courses in universities and technical schools often study the MIPS architecture.
Two companies have emerged that specialize in building multi-core devices using the MIPS architecture.
Both of these companies designed their cores in-house, just licensing the architecture instead of purchasing cores from MIPS.
There was speculation in the early 1990s that MIPS and other powerful RISC processors would overtake the Intel IA32 architecture.
This was encouraged by the support of the first two versions of Microsoft's Windows NT for Alpha, MIPS and PowerPC-and to a lesser extent the Clipper architecture and SPARC.
Through the 1990s, the MIPS architecture was widely adopted by the embedded market, including for use in computer networking, telecommunications, video arcade games, video game consoles, computer printers, digital set-top boxes, digital televisions, DSL and cable modems, and personal digital assistants.
In cellphone / PDA applications, MIPS has been largely unable to displace the incumbent, competing ARM architecture.
MIPS architecture processors include: IDT RC32438 ; ATI / AMD Xilleon ; Alchemy Au1000, 1100, 1200 ; Broadcom Sentry5 ; RMI XLR7xx, Cavium Octeon CN30xx, CN31xx, CN36xx, CN38xx and CN5xxx ; Infineon Technologies EasyPort, Amazon, Danube, ADM5120, WildPass, INCA-IP, INCA-IP2 ; Microchip Technology PIC32 ; NEC EMMA and EMMA2, NEC VR4181A, VR4121, VR4122, VR4181A, VR5432, VR5500 ; Oak Technologies Generation ; PMC-Sierra RM11200 ; QuickLogic QuickMIPS ESP ; Toshiba Donau, Toshiba TMPR492x, TX4925, TX9956, TX7901.
Its MIPS based supercomputers were withdrawn in 2005 when SGI made the strategic decision to move to Intel's IA-64 architecture.

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