This is especially applicable on superscalar x86 processors ( Pentium of 1993 and later ) where these exchange instructions are optimized down to a zero clock penalty.

This is especially applicable on superscalar x86 processors ( such as the Pentium of 1993 and later ) where these exchange instructions ( codes D9C8 .. D9CF < sub > h </ sub >) are optimized down to a zero clock penalty by using one of the integer paths for FXCH ST ( x ) in parallel with the FPU instruction.

0.007 seconds.