Page "Motorola 68060" Paragraph 3

The 68060 shares most architectural features with the P5 Pentium.

Both have a very similar superscalar in-order dual instruction pipeline configuration, and an instruction decoder which breaks down complex instructions into simpler ones before execution.

However, a significant difference is that the 68060 FPU is not pipelined and is therefore up to three times slower than the Pentium in floating point applications.

In contrast to that, integer multiplications and bit shifting instructions are significantly faster on the 68060.

An interesting feature of the 68060 is the ability to execute simple instructions in the address generation unit ( AGU ) and thereby supply the result two cycles before the ALU.

Another point of interest is that large amounts of commercial compiled code were analyzed for clues as to which instructions would be the best candidates for performance optimization.