[permalink] [id link]
** 24 bits per pixel support is mandatory in all resolutions supported.
from
Wikipedia
Some Related Sentences
** and 24
** August 24 ( Eastern Orthodox liturgics )
** Simon Magus ( 8: 9 – 24 )
** April 24 ( Eastern Orthodox liturgics )
** Jan Tyssowski was Dictator from 24 February 1846-2 March 1846.
** February 24 ( Eastern Orthodox liturgics )
** Vendémiaire in French ( from Latin vindemia, " grape harvest "), starting 22, 23 or 24 September
** Brumaire ( from French brume, " fog "), starting 22, 23 or 24 October
** Imperial: 2. 95 in x 1. 06 in x 5. 24 in
** International dollars ( purchasing power parity method ) $ 24. 69 billion ( 2007 est.
** Public administration, social and personal services 24. 8 %
** With China: $ 402. 6 billion, + 24. 2 % ( 2010 ), 48. 9 % share
** model 2: 80 × 24
** model 5: 132 × 27 or 80 × 24 ( switchable )
** June 24 ( Eastern Orthodox liturgics )
** July 24 ( Eastern Orthodox liturgics )
** January 24 ( Eastern Orthodox liturgics )
** May 24 ( Eastern Orthodox liturgics )
** Earliest day on which Corpus Christi can fall, while June 24 is the latest ; held on Thursday after Trinity Sunday.
** Order Peramelemorphia ( 24 species )
** March 24 ( Eastern Orthodox liturgics )
** November 24 ( Eastern Orthodox liturgics )
** October 24 ( Eastern Orthodox liturgics )
** Infantry Battalion 24 ( Bataillon d ' infanterie 24 )
** September 24 ( Eastern Orthodox liturgics ).
** and bits
** Parity flag in computing, indicates if the number of set bits is odd or even in the binary representation of the result of the last operation
** 8 bits per byte
** perform bitwise operations, taking the conjunction and disjunction of corresponding bits in a pair of registers, or the negation of each bit in a register
** Less than 24 bits per pixel is optional.
** Up to 48 bits per pixel are supported in dual link DVI, and is optional.
** WQXGA ( 2, 560 × 1, 600 ) @ 60 Hz with CVT-RB blanking ( 269 MHz ) ( This is for high end monitors when operating at greater than 24 bits per pixel.
** The segmented DAC, which combines the thermometer-coded principle for the most significant bits and the binary-weighted principle for the least significant bits.
** Optional boot code section with independent lock bits for protection
** Turnip cake ( 蘿蔔糕 lo4 baak6 gou1 ): cakes are made from mashed daikon radish mixed with bits of dried shrimp and pork sausage that are steamed and then cut into slices and pan-fried.
** Single precision – 36 bits: 1 sign bit, 8-bit characteristic, 27-bit mantissa
** Double precision – 72 bits: 1 sign bit, 11-bit characteristic, 60-bit mantissa
** ASCII – 9 bits per character ( right-most 8 used for an ASCII character ) four characters in each 36-bit word
** Receiving: the CAN controller stores received bits serially from the bus until an entire message is available, which can then be fetched by the host processor ( usually after the CAN controller has triggered an interrupt ).
** Sending: the host processor stores its transmit messages to a CAN controller, which transmits the bits serially onto the bus.
** An enhanced lossless macroblock representation mode allowing perfect representation of specific regions while ordinarily using substantially fewer bits than the PCM mode.
** Oreo Ice Cream Bar ( vanilla light ice cream mixed with Oreo pieces with a chocolate flavored coating with Oreo bits )
** 128-bit integers, memory addresses, or other data units are those that are at most 128 bits 16 octets wide
** 0 ... Device ID Register, 40 bits of read-only identification data
** 1 ... Debug Status and Control Register ( DSCR ), 32 bits used to operate the debug facilities
** 4 ... Instruction Transfer Register ( ITR ), 33 bits ( 32 instruction plus one status bit ) used to execute processor instructions while in a special " Debug Mode " ( see below )
** 5 ... Debug Communications Channel ( DCC ), 34 bits ( one long data word plus two status bits ) used for bidirectional data transfer to the core.
** 6 ... Embedded Trace Module ( ETM ), 40 bits ( 7 bit address, one 32-bit long data word, and a R / W bit ) used to control the operation of a passive instruction and data trace mechanism.
0.531 seconds.