Its microarchitecture, deemed P5, was Intel's fifth-generation and first superscalar x86 microarchitecture.

Intel's low-powered Bonnell microarchitecture employed in Atom processor cores also uses an in-order dual pipeline similar to P5.

The P5 microarchitecture was designed by the same Santa Clara team which designed the 386 and 486.

As a result, there were several variants of the P5 microarchitecture.

# REDIRECT P5 ( microarchitecture )# MMX

# REDIRECT P5 ( microarchitecture )

# REDIRECT P5 ( microarchitecture )

# REDIRECT P5 ( microarchitecture )

# REDIRECT P5 ( microarchitecture )

# REDIRECT P5 ( microarchitecture )# P55C, Tillamook

The invalid operand with locked CMPXCHG8B instruction bug, commonly referred to as the Pentium F00F bug ( as shorthand for, the hexadecimal encoding of one offending instruction ), is a design flaw in the majority of Intel Pentium, Pentium MMX, and Pentium OverDrive processors ( all in the P5 microarchitecture ).

# REDIRECT P5 ( microarchitecture )

* P5 ( microarchitecture )

# REDIRECT P5 ( microarchitecture )# P55C

The CPUs topped out at around 25 W heat output ( like the AMD K6 ), whereas the P5 Pentium produced around 15 W of waste heat at its peak.

Cyrix used a PR rating ( Performance Rating ) to relate their performance to the Intel P5 Pentium ( pre-P55C ), because a 6x86 at a lower clock rate outperformed the higher-clocked P5 Pentium.

More powerful 486 iterations such as the OverDrive and DX4 were less popular ( the latter available as an OEM part only ), as they came out after Intel had released the next generation P5 Pentium processor family.

Intel's Larrabee multicore architecture project uses a processor core derived from a P5 core ( P54C ), augmented by multithreading, 64-bit instructions, and a 16-wide vector processing unit.

The fourth generation competed with the P5 Pentium line, but it was not nearly as widely used as its predecessors, since much of the old 68000 marketplace was either defunct or nearly so ( as was the case with Atari and NeXT ), or converting to newer architectures ( PowerPC for the Macintosh and Amiga, SPARC for Sun, and MIPS for SGI ).

Processors that used Socket 7 are the AMD K5 and K6, the Cyrix 6x86 and 6x86MX, the IDT WinChip, the Intel P5 Pentium ( 2. 5 – 3. 5 V, 75 – 200 MHz ), the Pentium MMX ( 166 – 233 MHz ), and the Rise Technology mP6.

Luteal cells possess the necessary enzymes to convert cholesterol to pregnenolone ( P5 ), which is subsequently converted into P4.

The Land Rover became a runaway success ( despite Rover's reputation for making upmarket saloons, the utilitarian Land Rover was actually the company's biggest seller throughout the 1950s, ' 60s, and ' 70s ), as well as the P5 and P6 saloons equipped with a 3. 5L ( 215ci ) aluminium V8 ( the design and tooling of which was purchased from Buick ) and pioneering research into gas turbine-fueled vehicles.

Its regional center, Davao City, has an annual income of about P4. 13 billion in 2010, without introducing new taxes, making it as the most economically rich city both in Mindanao and Visayas and also outside Metro Manila after Makati ( P10. 1 billion ), Quezon City ( P9. 4 billion ), Manila ( P7. 3 billion ), and Pasig ( P5. 3 billion ).

If it is then assumed that the elementary opaque elements of all matter are identical ( i. e., having the same ratio of density to area ), it will follow that the shadow effect is, at least approximately, proportional to the mass ( P5 ).

* SR Metropol ( formerly SR P5 Radio Stockholm ), multicultural youth station for Stockholm ( available in Stockholm )

Bus routes 2, 3, 35, 37 ( at Lambeth Town Hall ), 45, 59, 109, 118, 133, 159, 196, 250, 322, 333, 345 ( at Brixton Police Station ), 355, 415, 432, P4, P5 ( at Electric Lane ); school routes 689 and 690 ; and Night routes N2, N3, N35, N109 and N133

* P5 ( comics ), a comic strip also known as Class Act in the UK comic The Dandy

London bus routes 35, 45, 345 ( 24 hour ), P4, P5 and night route N35.

These categories range from P1 ( Prototype size 1 ) to P5 ( prototype size 5 ), Hardware Plus ( smaller than a P1 with fewer building materials item selections ) and non-prototype ( usually stores that have moved into pre-existing locations or locations where large prototype stores will not fit, such as the 2-story stores ).

The AGP slot first appeared on x86 compatible system boards based on Socket 7 Intel P5 Pentium and Slot 1 P6 Pentium II processors.

The Intel P5 Pentium had two superscalar ALUs which could accept one instruction per clock each, but its FPU could not accept one instruction per clock.

The 6x86 and 6x86L weren't completely compatible with the Intel P5 Pentium instruction set and is not multi-processor capable.

The Intel P5 Pentium generation was a superscalar version of these principles.

The Pentium FDIV bug was a bug in the Intel P5 Pentium floating point unit ( FPU ).

Intel at first planned to demonstrate the P5 in June 1992 at the trade show PC Expo, and to formally announce the processor in September 1992, but design problems forced the demo to be cancelled, and the official introduction of the chip was delayed until the spring of 1993.

* March 22 – The Intel Corporation ships the first P5 Pentium chips.

Owners of personal computers containing Intel 80286 through P5 Pentium processors may be most familiar with these PGA packages, which were often inserted into ZIF sockets on motherboards.

The 4th generation 68060 shared most of the features of the Intel P5 architecture.

* Intel P5 Pentium ( co-existed with Pentium Pro for several years )

The socket supersedes the earlier Socket 5, and accepts P5 Pentium microprocessors manufactured by Intel, as well as compatibles made by Cyrix / IBM, AMD, IDT and others.

After abandoning the Intel P5 Pentium MMX CPU, Intel completely left the Socket 7 market to the manufacturers AMD, Cyrix and IDT.

Socket 5 was created for the second generation of Intel P5 Pentium processors operating at speeds from 75 to 120 MHz as well as certain Pentium OverDrive and Pentium MMX processors with core voltage 3. 3 V. Consisting of 320 pins, this was the first socket to use a staggered pin grid array, or SPGA, which allowed the chip's pins to be spaced closer together than earlier sockets.

During the development of what became the P5 Pentium microprocessor, the Intel Architecture Labs implemented one of the first, and at the time highest-quality, software-only video codecs, which was marketed as " Indeo Video ".