The first ( retroactively ) RISC-labeled processor ( IBM 801-IBMs Watson Research Center, mid-1970s ) was a tightly pipelined simple machine originally intended to be used as an internal microcode kernel, or engine, in CISC designs, but also became the processor that introduced the RISC idea to a somewhat larger public.

Increasingly, however, XSLT processors use optimization techniques found in functional programming languages and database query languages, such as static rewriting of an expression tree ( e. g., to move calculations out of loops ), and lazy pipelined evaluation to reduce the memory footprint of intermediate results ( and allow " early exit " when the processor can evaluate an expression such as without a complete evaluation of all subexpressions ).

A processor is said to be fully pipelined if it can fetch an instruction on every cycle.

To the extent that some instructions or some conditions require delays that inhibit fetching new instructions, the processor is not fully pipelined.

This assumption is not true on a pipelined processor.

Programs written for a pipelined processor deliberately avoid branching to minimize possible loss of speed.

The technique of self-modifying code can be problematic on a pipelined processor.

The advantages of a pipelined processor are diminished to the extent that execution encounters hazards that require execution to slow below its ideal rate.

Instructions in a pipelined processor are performed in several stages, so that at any given time several instructions are being processed in the various stages of the pipeline, such as fetch and execute.

* It offers all basic functions of a pipelined in-order processor.

In computer science, a decoupled architecture is a processor with out-of-order execution that separates the fetch and decode stages from the execute stage in a pipelined processor by using a buffer.

In a traditional non-optimized design, a particular instruction in a program sequence must be ( almost ) completed before the next can be issued for execution ; in a pipelined architecture, successive instructions can instead overlap in execution.

In multiprocessing, the processors can be used to execute a single sequence of instructions in multiple contexts ( single-instruction, multiple-data or SIMD, often used in vector processing ), multiple sequences of instructions in a single context ( multiple-instruction, single-data or MISD, used for redundancy in fail-safe systems and sometimes applied to describe pipelined processors or hyper-threading ), or multiple sequences of instructions in multiple contexts ( multiple-instruction, multiple-data or MIMD ).

In a pipelined write, the write command can be immediately followed by another command, without waiting for the data to be written to the memory array.

In a pipelined read, the requested data appears after a fixed number of clock cycles after the read command ( latency ), clock cycles during which additional commands can be sent.

Scheduling is a speed optimization that can have a critical effect on pipelined machines.

The SMTP protocol can allow several SMTP commands to be placed in one network packet and " pipelined ".

SSE stages can be pipelined with different contexts, or computed in parallel with the outputs averaged.

The FPU is pipelined and can execute single precision ( 32-bit ) and double precision ( 64-bit ) instructions.

Sequences of GET and HEAD requests can always be pipelined.

A sequence of other idempotent requests like GET, HEAD, PUT and DELETE can be pipelined or not depending on whether requests in the sequence depend on the effect of others.

If, as in the previous example, < tt > x </ tt >, < tt > y </ tt >, < tt > t1 </ tt >, and < tt > t2 </ tt > are all located on the same remote machine, a pipelined implementation can compute < tt > t3 </ tt > with one round-trip instead of three.

Unlike most modern CPU designs, functional units were not pipelined ; the functional unit would become busy when an instruction was " issued " to it and would remain busy for the entire time required to execute that instruction.

Naturally, accomplishing this requires additional circuitry, so pipelined processors are more complex than subscalar ones ( though not very significantly so ).

The main purpose of predication is to avoid jumps over very small sections of program code, increasing the effectiveness of pipelined execution and avoiding problems with the cache.

The advantage of the bitboard representation is that it takes advantage of the essential logical bitwise operations available on nearly all CPUs that complete in one cycle and are full pipelined and cached etc.

The first highly ( or tightly ) pipelined x86 implementations, the 486 designs from Intel, AMD, Cyrix, and IBM, supported every instruction that their predecessors did, but achieved maximum efficiency only on a fairly simple x86 subset that was only a little more than a typical RISC instruction set ( i. e. without typical RISC load-store limitations ).

However, modern x86 processors also ( typically ) decode and split instructions into dynamic sequences of internally buffered micro-operations, which not only helps execute a larger subset of instructions in a pipelined ( overlapping ) fashion, but also facilitates more advanced extraction of parallelism out of the code stream, for even higher performance.

It has proven much easier to design pipelined CPUs if the only addressing modes available are simple ones.

Most modern CPUs ( even embedded CPUs ) are now pipelined, and microcoded CPUs with no pipelining are seen only in the most area-constrained embedded processors.

Some RISC proponents had argued that the " complicated " x86 instruction set would probably never be implemented by a tightly pipelined microarchitecture, much less by a dual pipeline design.

; Instruction scheduling: Instruction scheduling is an important optimization for modern pipelined processors, which avoids stalls or bubbles in the pipeline by clustering instructions with no dependencies together, while being careful to preserve the original semantics.

Note that Windows 2008 introduced pipelined TFTP as part of Windows Deployment Services ( WDS ) and uses an 8 packet window by default.

The pipelined control was designed by faculty member Donald B. Gillies.

This helps to eliminate problems caused by the propagation delay of the clock wiring, and allows the illusion of concurrent reads and writes ( as seen on the bus, although internally the memory still has a conventional single port-operations are pipelined but sequential ).

In other words, a pipelined process outputs finished items at a rate determined by its slowest part.

The ILLIAC II was the first transistorized and pipelined supercomputer built by the University of Illinois.

How would an external observer know whether the processing of a message by an Actor has been pipelined?

Don Gillies took over the project in the spring of 2000 and enhanced the protocol to allow pipelined ICAP servers and to support all 3 encapsulations of HTTP allowed by HTTP 1. 1.

* the DAISY Pipeline, a cross-platform " open source framework for document-and DTB-related pipelined transformations ", developed by the DAISY Consortium,

For instance, the multiplication and addition units were implemented as separate hardware, so the results of one could be internally pipelined into the next, the instruction decode having already been handled in the machine's main pipeline.

The branch delay slot is a side effect of pipelined architectures due to the branch hazard, i. e. the fact that the branch would not be resolved until the instruction has worked its way through the pipeline.

Due to the reduced complexity of the Classic RISC pipeline, the pipelined core and an instruction cache could be placed on the same size die that would otherwise fit the core alone on a CISC design.