MMX is a SIMD instruction set designed by Intel, introduced in 1997 for the Pentium MMX microprocessor.

MMX is typically used for video processing ( in " multimedia " applications for instance ).

However, one of the main concepts of the MMX instruction set is the concept of packed data types, which means instead of using the whole register for a single 64-bit integer ( quadword ), one may use it to contain two 32-bit integers ( doubleword ), four 16-bit integers ( word ) or eight 8-bit integers ( byte ).

As such, it uses exactly the same register naming convention as MMX, that is MM0 through MM7.

MMX is a single instruction, multiple data ( SIMD ) instruction set designed by Intel, introduced in 1996 with their P5-based Pentium line of microprocessors, designated as " Pentium with MMX Technology ".

MMX is a processor supplementary capability that is supported on recent IA-32 processors by Intel and other vendors.

The main usage of the MMX instruction set is based on the concept of packed data types, which means that instead of using the whole register for a single 64-bit integer, two 32-bit integers, four 16-bit integers, or eight 8-bit integers may be processed concurrently.

However VIS is not an instruction toolkit like Intel's MMX and SSE.

This design is very different from comparable extensions on CISC processors, such as MMX, SSE, SSE2, SSE3, SSE4, 3DNow !.

In this respect VIS is more similar to the design of MMX than other SIMD architectures such as SSE / SSE2 / AltiVec.

This system is the primary Windows 2000 Server having the task to control and administer the usage of ( 240 ) Windows NT Workstations ( Pentium MMX ) located in five computer labs at the Computer Center.

In practice it is typical to use instructions which will execute on anything later than an Intel 80386 ( or fully compatible clone ) processor or else anything later than an Intel Pentium ( or compatible clone ) processor but in recent years various operating systems and application software have begun to require more modern processors or at least support for later specific extensions to the instruction set ( e. g. MMX, 3DNow !, SSE / SSE2 / SSE3 ).

It extends the earlier SSE instruction set, and is intended to fully supplant MMX.

However, this is over-shadowed by the value of being able to perform MMX operations on the wider SSE registers.

Therefore, it is possible to convert all existing MMX code to an SSE2 equivalent.

Since an XMM register is twice as long as an MMX register, loop counters and memory access may need to be changed to accommodate this.

Since the problem is not locally apparent in the MMX code, the bug can be very time consuming to find and correct.

Basic system requirements for version 1. x and 2. x are relatively low: a PC with a Pentium MMX ( i586 ) class CPU and 64 MB of RAM is sufficient.

Some desktop Linux distributions such as Fedora Core 6, Ubuntu and openSUSE do not enable the HIGHMEM64 option by default, which is required to gain access to the NX bit in 32-bit mode, in their default kernel ; this is because the PAE mode that is required to use the NX bit causes pre-Pentium Pro ( including Pentium MMX ) and Celeron M and Pentium M processors without NX support to fail to boot.

These bits are set to all ones by any MMX instruction, which correspond to the floating point representation of NaNs or infinities.

The first addition allowed offloading of basic floating-point operations from the x87 stack and the second made MMX almost obsolete and allowed the instructions to be realistically targeted by conventional compilers.

AMD and Intel settled, with AMD acknowledging MMX as a trademark owned by Intel, and with Intel granting AMD rights to use the MMX trademark as a technology name, but not a processor name.

SSE addressed the core shortcomings of MMX ( inability to mix integer-SIMD ops with any floating-point ops ) by creating a new 128-bit wide register file ( XMM0-XMM7 ) and new SIMD instructions for it.

) However, since processor support for any SSE revision also implies support for MMX, the removal does not limit the types of data types usable by x86 SIMD.

The addition of integer support in SSE2 made MMX largely redundant, though further performance increases can be attained in some situations by using MMX in parallel with SSE operations.

User application uptake of the x86 extensions has been slow with even bare minimum baseline MMX and SSE support ( in some cases ) not being supported by applications some 10 years after these extensions became commonly available.

These were replaced by Pentium OverDrive MMX, which also upgraded the Pentium 120-200 MHz to the faster with MMX technology.

Lazy Assembler is a freeware assembler not associated with Borland which is compatible with TASM ideal mode but with support for newer instructions not supported by TASM: MMX, SSE, SSE2, SSE3 ( PNI ), SSE4 ( MNI ), 3DNow! Pro.

In 1999 Intel released macros for SIMD and MMX instructions, which were shortly after supported natively by MASM.

In 2000, a fast implementation of the Smith – Waterman algorithm using the SIMD technology available in Intel Pentium MMX processors and similar technology was described in a publication by Rognes and Seeberg.

Saturation arithmetic operations are available on many modern platforms, and in particular was one of the extensions made by the Intel MMX platform, specifically for such signal processing applications.

Additions included DSP instructions and an implementation of the extended MMX subset of Intel SSE.

Intel Pentium MMX microarchitecture.

The MMX instruction set was developed from a similar concept first used on the Intel i860.

AMD, during one of its numerous court battles with Intel, produced marketing material from Intel indicating that MMX stood for " Matrix Math Extensions ".

In 1997, Intel filed suit against AMD and Cyrix Corp. for misuse of its trademark MMX.

iwMMXt stands for " Intel Wireless MMX Technology ".

* Intel Pentium Processor with MMX Technology Documentation

id: Intel MMX

nl: MMX ( Intel )

Processors that used Socket 7 are the AMD K5 and K6, the Cyrix 6x86 and 6x86MX, the IDT WinChip, the Intel P5 Pentium ( 2. 5 – 3. 5 V, 75 – 200 MHz ), the Pentium MMX ( 166 – 233 MHz ), and the Rise Technology mP6.