An interesting aspect of the PA-RISC line is that most of its generations have no Level 2 cache.

The ISA was extended in 1996 to 64-bits, with this revision named PA-RISC 2. 0.

The first PA-RISC 2. 0 implementation was the PA-8000, which was introduced in January 1996.

; 10. 20 ( 1996 ): This release included support for PA-RISC 2. 0 processors that support 64-bit data registers.

Version 2. 2 has been ported to the Apollo, DECstation, Data General AViiON, HP 9000 Series 300, Multimax, NeXT, PA-RISC, RS / 6000, Sequent Symmetry, SGI IRIS, Sun-3, Sun-4 and others.

* PA-RISC 2. 0 Series 996, A and N class and the 9x9 series

The zx1 chipset is chipset for the Itanium 2 and PA-RISC microprocessors from Hewlett Packard.

Towards the end of Commodore's time in charge of Amiga development there were suggestions that Commodore intended to move away from the 68000 series to higher performance RISC processors, such as the PA-RISC.

GDB target processors ( as of 2003 ) include: Alpha, ARM, AVR, H8 / 300, System / 370, System 390, X86 and its 64-bit extension X86-64, IA-64 " Itanium ", Motorola 68000, MIPS, PA-RISC, PowerPC, SuperH, SPARC, and VAX.

The success of this initial processor version was limited to replacing PA-RISC in HP systems, Alpha in Compaq systems and MIPS in SGI systems, though IBM also delivered a supercomputer based on this processor.

NeXTSTEP 3. x was later ported to PA-RISC and SPARC-based platforms, for a total of four versions: NeXTSTEP / NeXT ( for NeXT's 68k " black boxes "), NeXTSTEP / Intel, NeXTSTEP / PA-RISC and NeXTSTEP / SPARC.

PA-RISC is an instruction set architecture ( ISA ) developed by Hewlett-Packard.

PA-RISC has been succeeded by the Itanium ( originally IA-64 ) ISA jointly developed by HP and Intel.

HP stopped selling PA-RISC-based HP 9000 systems at the end of 2008 but will support servers running PA-RISC chips until 2013.

HP planned to use PA-RISC to move all of their non-PC compatible machines to a single RISC CPU family.

The HP 9000 machines were soon upgraded with the PA-RISC processor as well, running the HP-UX version of UNIX.

Other operating systems ported to the PA-RISC architecture include Linux, OpenBSD, NetBSD and NEXTSTEP.

Another innovation of the PA-RISC was the addition of vectorized instructions ( SIMD ) in the form of MAX, which were first introduced on the PA-7100LC.

Well known RISC families include DEC Alpha, AMD 29k, ARC, ARM, Atmel AVR, Blackfin, MIPS, PA-RISC, Power ( including PowerPC ), SuperH, and SPARC.

In 1986 Hewlett Packard started using an early implementation of their PA-RISC in some of their computers.

Recent versions support the HP 9000 series of computer systems, based on the PA-RISC processor architecture, and HP Integrity systems, based on Intel's Itanium architecture.

* PA-RISC 1. 0 Series 925, 930, 935, 949, 950, 955, 960, 980

* Hewlett-Packard's PA-RISC, also known as HP-PA, ( discontinued at the end of 2008 )

HP also released a port of OSF / 1 to the early HP 9000 / 700 workstations based on the PA-RISC 1. 1 architecture.

This is different from the protection key mechanism used by processors such as the Intel Itanium and the Hewlett-Packard Precision Architecture ( HP / PA, also known as PA-RISC ), which are associated

Weitek also worked with HP on the design of their latest PA-RISC design, and sold their own version known as the RISC 8200 which was sold as an embedded design and had some use in laser printers.

Its modern variants NetBSD and OpenBSD also support various HP 9000 models, both Motorola 68k and PA-RISC based.

Tandem added support for 32-bit addressing in its second machine ; HP 3000 lacked this until its PA-RISC generation.

PA-RISC –

The HP 3000 series did not add paging until the PA-RISC generation, 10 years later.

SIMD instructions can be found, to one degree or another, on most CPUs, including the IBM's AltiVec and SPE for PowerPC, HP's PA-RISC Multimedia Acceleration eXtensions ( MAX ), Intel's MMX and iwMMXt, SSE, SSE2, SSE3 SSSE3 and SSE4. x, AMD's 3DNow !, ARC's ARC Video subsystem, SPARC's VIS and VIS2, Sun's MAJC, ARM's NEON technology, MIPS ' MDMX ( MaDMaX ) and MIPS-3D.

The ARIES fast interpreter emulates a complete set of non-privileged PA-RISC instructions with no user intervention.

* HP-UX ( except for 32-bit PA-RISC programs which continue to use SOM )

Servers use those processors and other readily available non-x86 processor choices, including the Sun Microsystems UltraSPARC, Fujitsu SPARC64 III and later, SGI MIPS, Intel Itanium, Hewlett Packard PA-RISC, Hewlett-Packard ( merged with Compaq which acquired first Digital Equipment Corporation ) DEC Alpha, IBM POWER and Apple Computer PowerPC ( specifically G4 and G5 series, as well as earlier PowerPC 604 and 604e series ) processors.

It runs the HP 3000 family of computers, which originally used HP custom 16 bit stack architecture CISC CPUs and were later migrated to PA-RISC where the operating system was called MPE / XL.

A link register, in many instruction set architectures such as the PowerPC, ARM, and the PA-RISC, is a special purpose register which holds the address to return to when a function call completes.

W ^ X is relatively simple on processors which support fine-grained page permissions, such as Sun's SPARC and SPARC64, AMD's AMD64, Hewlett-Packard's PA-RISC, and HP's ( originally Digital Equipment Corporation's ) Alpha ; some early Intel 64 processors lacked the NX bit required for W ^ X, but this appeared in later chips.

ISCABBS originally supported over a thousand simultaneous users on a 50 MHz PA-RISC system with 64MB of RAM, which ran HP-UX.

It is presented mainly for ' academic interest ' due to its complexity, specificity to ISCA BBSes PA-RISC hardware, and poor documentation ; however, at least one branch from an earlier version of DOC is being developed under the name vDOC ( or variant DOC ), which is known to work on Linux, Solaris, and FreeBSD systems.

It did provide support for running PA-RISC compiled applications on Itanium systems, and for Veritas Volume Manager 3. 1.

In September 2004 the OS was updated to provide support for both Itanium and PA-RISC systems.

* Precision Architecture, former name for PA-RISC, a reduced instruction set architecture developed by Hewlett-Packard

* Multimedia Acceleration eXtensions, for HP PA-RISC

The second capability, by itself, is less noteworthy, as major RISC architectures ( such as SPARC, Alpha, PA-RISC, PowerPC, MIPS ) have been 64-bit for many years.

The Apollo engineering center took over PA-RISC workstation development and Apollo became an HP workstation brand name ( HP Apollo 9000 ) for a while.

Tandem could not use HP's PA-RISC or Sun's SPARC CPUs, for business reasons.

The HP 3000 family's generations were divided into the " Classic " ( 16-bit ) and then " XL " ( later IX-32-bit ) families following the introduction of systems based on HP's PA-RISC chips for 3000s in early 1987.

From the mid-1980s onwards, HP started to switch over to its own microprocessors based on its proprietary PA-RISC ISA, for the Series 600, 700, 800, and later lines.

The ' rp ' prefix signified a PA-RISC architecture, while ' rx ' was used for IA-64-based systems, later rebranded HP Integrity.

The Runway bus is a front side bus developed by Hewlett-Packard for use by its PA-RISC microprocessor family.

This led to virtually every Unix vendor hurrying for a RISC design of their own, leading to designs like the DEC Alpha and PA-RISC, while SGI purchased MIPS Computer Systems.