Sometimes it is enough to ground the CLK or DTA line of the I²C bus of the EEPROM at the right moment during boot, this requires some precise soldering on SMD parts.

Operation of a parallel EEPROM is simple and fast when compared to serial EEPROM, but these devices are larger due to the higher pin count ( 28 pins or more ) and have been decreasing in popularity in favor of serial EEPROM or Flash.

Some ( homebrew ) carts with EEPROM to save hi-scores.

In 1993, the introduction of EEPROM memory allowed microcontrollers ( beginning with the Microchip PIC16x84 )

The SL and TL were also shipped with MS-DOS 3. 3 and DeskMate 3 in ROM, and featured an EEPROM memory chip to store BIOS settings ( which enabled similar functionality to today's CMOS NVRAMs, so that startup options could be saved ).

It was developed from EEPROM ( electrically erasable programmable read-only memory ) and must be erased in fairly large blocks before these can be rewritten with new data.

The OP-Code is usually the first 8-bits input to the serial input pin of the EEPROM device ( or with most I²C devices, is implicit ); followed by 8 to 24 bits of addressing depending on the depth of the device, then data to be read or written.

DV cassettes can come with a memory-in-cassette ( MIC ) low capacity EEPROM memory chip.

Features of the modern 8051 include built-in reset timers with brown-out detection, on-chip oscillators, self-programmable Flash ROM program memory, built-in external RAM, extra internal program storage, bootloader code in ROM, EEPROM non-volatile data storage, I²C, SPI, and USB host interfaces, CAN or LIN bus, PWM generators, analog comparators, A / D and D / A converters, RTCs, extra counters and timers, in-circuit debugging facilities, more interrupt sources, and extra power saving modes.

Since the number of writes to EEPROM is not unlimited — Atmel specifies 100, 000 write cycles in their datasheets — a well designed EEPROM write routine should compare the contents of an EEPROM address with desired contents and only perform an actual write if the contents need to be changed.

After the START, the master sends the chip's bus address with the direction bit clear ( write ), then sends the two byte address of data within the EEPROM and then sends data bytes to be written starting at that address, followed by a STOP.

After a START, the master first writes that chip's bus address with the direction bit clear ( write ) and then the two bytes of EEPROM data address.

The EEPROM will then respond with the data bytes beginning at the specified EEPROM data address — a combined message, first a write then a read.

The PIC16F84 / PIC16F84A is an improved version of the PIC16C84, and almost completely compatible, with better program security and using flash memory instead of EEPROM memory for program memory.

GlideSensor ’ s mixed-mode ASIC controller was designed to blend the performance of GlidePoint with a low-voltage, low-power EEPROM programmable processor.

Lattice Semiconductor introduced the generic array logic ( GAL ) family in 1985, with functional equivalents of the " V " series PALs that used reprogrammable logic planes based on EEPROM ( electrically eraseable programmable read-only memory ) technology.

The on-board computer was a Harris 80C86 with 64 kilobytes of EEPROM and 64 kilobytes of static RAM.

A GNX specific EEPROM, low-restriction exhaust with dual mufflers, reprogrammed Turbo Hydramatic 200-4R transmission with a custom torque converter and transmission cooler, and unique differential cover / panhard bar included more of the performance modifications.

PICAXE microcontrollers are pre-programmed with an interpreter similar to the BASIC Stamp but using internal EEPROM instead, thus reducing cost.

Made of PC with the dimensions in the ISO / IEC 7816 ID-1 format ( standard credit card format ), the initial card had a 32kb EEPROM ( Electronically Erasable Programmable Read-Only Memory ) embedded chip running on M-COS ( MyKad Chip Operating System ).

* Non-volatile random access memory ( NVRAM ), usually in the form of static RAM backed up with battery power ( battery RAM ), or an electrically erasable programmable ROM ( EEPROM ).

It can only be accessed the same way an external peripheral device is, using special pointer registers and read / write instructions which makes EEPROM access much slower than other internal RAM.

* Memory blocks including a selection of ROM, RAM, EEPROM and flash memory.

Modern ASICs often include entire microprocessors, memory blocks including ROM, RAM, EEPROM, Flash and other large building blocks.

The typical ROM size is between and, typical RAM size is between and, and typical EEPROM size is between and.

" It features a 25 MHz HCS12 CPU, 64 kB of FLASH EEPROM, 8 kB of RAM, and an Ethernet 10 / 100 Mbit / s controller.

* Paged memory regions in the 64KByte local map: PPAGE for paged program data, RPAGE for paged RAM, EPAGE for paged EEPROM / flash

The UICC smart card consists of a CPU, ROM, RAM, EEPROM and I / O circuits.

Cell 0 was “ ROM ”, always containing a numeric " 1 "; cells 1 to 98 were “ RAM ”; available for instructions and data ; and cell 99 could best be described as “ EEPROM ”.

Data storage can be provided by magnetic tape, battery-backed RAM and, more recently, non-volatile EEPROM or Flash Memory overwritten in a FIFO continuous loop.

Flash memory now costs far less than byte-programmable EEPROM and has become the dominant memory type wherever a significant amount of non-volatile, solid state storage is needed.

Each EEPROM device typically has its own set of OP-Code instructions to map to different functions.

The Electrically Erasable Programmable Read-Only Memory ( EEPROM ) was developed to provide an electrical erase function and has now mostly displaced ultraviolet-erased parts.

It also has a 64 byte EEPROM for storage of user data.

It is common practice to use rewritable non-volatile memory – such as UV-EPROM or EEPROM – for the development phase of a project, and to switch to mask ROM when the code has been finalized.

The functionality of the MK-61 is identical to that of the MK-52, except the MK-52 has an internal non-volatile EEPROM memory module, for permanent data storage and also has the capability of using external EEPROM modules.

The system also has a mini USB interface for programming the system, an RJ-11 Ethernet port, and a 128K serial Flash EEPROM for storage.

The term remains in wide use but it has grown into a misnomer: nonvolatile storage in contemporary computers is often in EEPROM or flash memory ( like the BIOS code itself ); the remaining usage for the battery is then to keep the real-time clock going.

In yet other cases, the EEPROM chip has to be desoldered and the data in it manually edited using a programmer.

Like flash memory, EEPROM can maintain its contents when electrical power is removed.

Its products include microcontrollers ( including 8051 derivatives, AT91SAM and AT91CAP ARM-based micros, and its own Atmel AVR and AVR32 architectures ), radio frequency ( RF ) devices, EEPROM and flash memory devices ( including DataFlash-based memory ), and a number of application-specific products.