While I²C only arbitrates between masters, SMBus uses arbitration in three additional contexts, where multiple slaves respond to the master, and one gets its message through.

Other than to indicate a slave's device-busy condition, SMBus also uses the NACK mechanism to indicate the reception of an invalid command or data.

SMBus, defined by Intel in 1995, is a subset of I²C that defines the protocols more strictly.

Accordingly, modern I²C systems incorporate policies and rules from SMBus, sometimes supporting both I²C and SMBus with minimal re-configuration required.

With only a few exceptions, neither I²C nor SMBus define message semantics, such as the meaning of data bytes in messages.

Those exceptions include messages addressed to the I²C general call address ( 0x00 ) or to the SMBus Alert Response Address ; and messages involved in the SMBus Address Resolution Protocol ( ARP ) for dynamic address allocation and management.

I²C EEPROMs smaller than 32 kbits, such as 2 kbit 24c02 ones, are often used on SMBus with inefficient single byte data transfers.

While SMBus is derived from I²C, there are several major differences between the specifications of the two busses in the areas of electricals, timing, protocols and operating modes.

When mixing devices, the I²C specification defines the V < sub > DD </ sub > to be 5. 0 V ± 10 % and the fixed input levels to be 1. 5 and 3. 0 V. Instead of relating the bus input levels to V < sub > DD </ sub >, SMBus defines them to be fixed at 0. 8 and 2. 1 V. This SMBus specification allows for bus implementations with V < sub > DD </ sub > ranging from 3 to 5 V.

SMBus has a ‘ High Power ’ version 2. 0 that includes a 4 mA sink current that cannot be driven by I²C chips unless the pull-up resistor is sized to I²C-bus levels.

The SMBus clock is defined from 10 – 100 kHz while I²C can be 0 – 100 kHz, 0 – 400 kHz, 0 – 1 MHz and 0 – 3. 4 MHz, depending on the mode.

This means that an I²C bus running at less than 10 kHz will not be SMBus compliant since the SMBus devices may time out.

* SMBus defines a clock low time-out, TTIMEOUT of 35 ms. I²C does not specify any timeout limit.

* The SMBus time-out specifications do not preclude I²C devices co-operating reliably on the SMBus.

The SMBus protocols are a subset of the data transfer formats defined in the I²C specifications.

I²C devices that can be accessed through one of the SMBus protocols are compatible with the SMBus specifications.

I²C devices that do not adhere to these protocols cannot be accessed by standard methods as defined in the SMBus and ACPI specifications.

( That data transfer part of the protocol also makes trouble for SMBus, since the data bytes are not preceded by a count and more than 32 bytes can be transferred at once.

The System Management Bus ( abbreviated to SMBus or SMB ) is a single-ended simple two-wire bus for the purpose of lightweight communication.

SMBus ‘ high power ’ devices and I²C-bus devices will work together if the pull-up resistor is sized for 3 mA.

* SMBus specifies TLOW: SEXT as the cumulative clock low extend time for a slave device.

* SMBus specifies TLOW: MEXT as the cumulative clock low extend time for a master device.

There is no limit in the I²C-bus protocol as to how long this delay can be, whereas for an SMBus system, it would be limited to 35 ms.

The Smart Battery System define the SMBus connection, the data that can be sent over the connection ( Smart Battery Data or SBD ), the Smart Battery Charger, and a computer BIOS interface for control.

* Packet Error Checking, a CRC-8 checksum for SMBus communication

Not only can the communication lines be shared among 8 memory modules, the same SMBus is commonly used on motherboards for system health monitoring tasks such as reading power supply voltages, CPU temperatures, and fan speeds.

SMBus also defines a less common " Host Notify Protocol ", providing similar notifications but passing more data and building on the I²C multi-master mode.

A special integrated circuit in the battery pack monitors the battery and reports information to the SMBus.

One purpose of SMBus is to promote robustness and interoperability.

SMBus is restricted to nine of those structures, such as read word N and write word N, involving a single slave.

PMBus extends SMBus with a Group protocol, allowing multiple such SMBus transactions to be sent in one combined message.

Most SMBus operations involve single byte commands.

( Accordingly, these EEPROMs aren't usable by pure SMBus hosts, which only support single byte commands or addresses.

( That's another incompatibility with SMBus: SMBus devices must always respond to their bus addresses.

To ensure a minimum bus throughput, SMBus places limits on how far clocks may be stretched.

It seizes the bus and writes a 3-byte message to the reserved " SMBus Host " address ( 0x08 ), passing its address and two bytes of data.

In this case, the host performs a 1-byte read from the reserved " SMBus Alert Response Address " ( 0x0c ), which is a kind of broadcast address.

* SMBus.

The SMBus is used to communicate with other devices on the motherboard ( e. g., system temperature sensors, fan controllers ).

PCI add-in cards may connect to a SMBus segment.

The SMBus is generally not user configurable or accessible.