Late designs in several processor families exhibit CMP, including the x86-64 Opteron and Athlon 64 X2, the SPARC UltraSPARC T1, IBM POWER4 and POWER5, as well as several video game console CPUs like the Xbox 360's triple-core PowerPC design, and the PS3's 7-core Cell microprocessor.

This design became the basis of the commercial SPARC processor design.

In the meantime, the Berkeley RISC effort had become so well known that it eventually became the name for the entire concept and in 1987 Sun Microsystems began shipping systems with the SPARC processor, directly based on the Berkeley RISC-II system.

Sun products included computer servers and workstations built on its own RISC-based SPARC processor architecture as well as on x86 based AMD's Opteron and Intel's Xeon processors ; storage systems ; and a suite of software products including the Solaris operating system, developer tools, Web infrastructure software, and identity management applications.

The most recent commercial iterations of the SPARC processor design are the Fujitsu Laboratories Ltd .' s " Venus " 128 GFLOP SPARC64 VIIIfx introduced June 2009, which is used in the 8 petaFLOPS Japanese supercomputer " K computer ", and the SPARC T4 introduced by Oracle Corporation in September 2011 ; both are 8 core devices running at 2. 0GHz and over 2. 5GHz respectively.

In 2002, the SPARC Joint Programming Specification 1 ( JPS1 ) was released by Fujitsu and Sun, describing processor functions which were identically implemented in the CPUs of both companies (" Commonality ").

Meiko also produced a SPARC processor board, the MK083, which allowed the integration of the SunOS operating system into the Computing Surface architecture, similarly to the In-Sun Computing Surface.

MeikOS was made obsolete by the introduction of the In-Sun Computing Surface and the Meiko MK083 SPARC processor board, which allowed SunOS and SVCS ( Sun Virtual Computing Surfaces, later developed as VCS ) to take over the roles of MeikOS and M²VCS respectively.

Although many people reported that Sun Microsystems ' UltraSPARC T1 ( known as " Niagara " until its 14 November 2005 release ) and the now defunct processor codenamed " Rock " ( originally announced in 2005, but after many delays cancelled in 2009 ) are implementations of SPARC focused almost entirely on exploiting SMT and CMP techniques, Niagara is not actually using SMT.

In other instruction sets, a NOP has to be simulated by executing an instruction having operands that cause the same effect ( e. g., on the SPARC processor, the instruction is the recommended solution ).

In the early 1990s they also introduced the SPARC POWER µP ( as in “ power-up ”, and technically referred to as WTL 8601 ), a pin-compatible version of the SPARC processor.

The page-level mechanism has been around for years in various other processor architectures such as DEC's ( now HP's ) Alpha, Sun's SPARC, and IBM's System / 370-XA, System / 390, z / Architecture and PowerPC.

LCC can generate code for several processor architectures, including Alpha, SPARC, MIPS, and x86 ; there is also an LCC backend that generates Microsoft's Common Intermediate Language.

The LEON3 is a synthesisable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture.

The RISC design was later commercialized as the SPARC processor, and inspired the landmark DEC Alpha architecture.

RISC is less famous, but more influential, for being the basis of the commercial SPARC processor design from Sun Microsystems.

Instead of saving out all of the processor state — the normal procedure in the case of a trap into the kernel — Spring only saved out the top 16 SPARC registers, a number which was defined by specific implementation details of the SPARC architecture.

Sun SPARCstation 1 + " pizzabox ", 25 MHz SPARC processor, early 1990s

T1 is the first SPARC processor that supports the Hyper-Privileged execution mode.

Single threaded application weakness was mitigated with the follow-on SPARC T4 processor.

" A 16-core SPARC SoC processor enables up to 512 threads in a 4-way glueless system to

RISC processors using 32-bit instructions are usually 3-operand machines, such as processors implementing the Power Architecture, the SPARC architecture, the MIPS architecture, the ARM architecture, and the AVR32 architecture.

This table contains specifications for certain SPARC processors: frequency ( megahertz ), architecture version, release year, number of threads ( threads per core multiplied by the number of cores ), fabrication process ( micrometers ), number of transistors ( millions ), die size ( square millimetres ), number of I / O pins, dissipated power ( watts ), voltage, and cache sizes — data, instruction, L2 and L3 ( kibibytes ).

The SPARC architecture has been licensed to many companies who have developed and fabricated implementations such as:

The second capability, by itself, is less noteworthy, as major RISC architectures ( such as SPARC, Alpha, PA-RISC, PowerPC, MIPS ) have been 64-bit for many years.

It works on many architectures, including x86, ARM, PowerPC, AMD64, IA-64, SPARC, Alpha, PA-RISC, MIPS and Motorola 68k.

Has been ported to many operating systems including Macintosh on PPC and x86, Linux on x86, x86-64 & PPC, Sun Solaris on SPARC and Windows on x86.

On 32-bit SPARC V8 systems, a complete round-trip call using the fast-path took just over 100 instructions, making it many times faster than a typical Mach call.

Other architectures ( such as SPARC ) have a register with the same purpose but another name ( in this case, " output register 7 ").

In SPARC Version 8, the floating point register file has 16 double precision registers.

SPARC Version 9 added 16 more double precision registers ( which can also be accessed as 8 quad precision registers ), but these additional registers can not be accessed as single precision registers.

MMX has only 8 registers shared with the FPU stack, while SPARC processors have 32 registers, also aliased to the double-precision ( 64-bit ) floating pointer registers.

VIS re-uses existing SPARC V9 64-bit floating point registers to hold multiple 8, 16, or 32-bit integer values.

Processors such as PowerPC or SPARC save state to predefined and reserved machine registers.

By comparison, the Sun Microsystems SPARC architecture provides simultaneous visibility into four sets of eight registers each.

As the SPARC ISA uses register windows, of which the UltraSPARC has eight, the actual number of registers is 144.

Values being returned from the routines would be placed in the " global page ", the top eight registers in the SPARC ( for instance ).

A routine using only one local variable would still use up eight registers on the SPARC, wasting this expensive resource.

In comparison the SPARC had 128 registers in total, and the global set was a standard window of eight.

Other processors like PowerPC or SPARC generally save state to predefined and reserved machine registers.

SPARC processors have four levels of such registers, i. e. they have a 4-window register system.

The SPARC ISA defines register windows, in which the 5-bit architectural names of the registers actually point into a window on a much larger register file, with hundreds of entries.