When a caching ( recursive ) nameserver queries the authoritative nameserver for a resource record, it will cache that record for the time ( in seconds ) specified by the TTL.

When a file is written to the buffer cache, rather than allocating extents for the data, XFS simply reserves the appropriate number of file system blocks for the data held in memory.

When an XFS filesystem is used on a logical device provided by a hardware RAID controller with battery backed cache, this feature can cause significant performance degradation, as the filesystem code is not aware that the cache is nonvolatile, and if the controller honors the flush requests, data will be written to physical disk more often than necessary.

When a write operation is observed to a location that a cache has a copy of, the cache controller invalidates its own copy of the snooped memory location.

When a write operation is observed to a location that a cache has a copy of, the cache controller updates its own copy of the snarfed memory location with the new data.

When Silver escapes at the end of the novel, he takes " three or four hundred guineas " of the treasure with him, thus becoming one of only two former members of Captain Flint's crew to get his hands on a portion of the recovered treasure ; a separate cache of bar silver is apparently left on the island.

When a failure is cached, the program should provide a clear indication of what must be done to clear the cache, in addition to a description of the cause of the error.

When the table fills up, less-used positions are removed to make room for new ones ; this makes the transposition table a kind of cache.

When this thread encounters a high latency event ( L2 cache miss, etc.

When equipped with a 1MB L3 cache ( on the motherboard ) the 400 and 450 MHz K6-IIIs is claimed by Ars Technica to often outperform the hugely higher-priced Pentium III " Katmai " 450-and 500-MHz models, respectively.

When an instruction is actually needed, the instruction can be accessed much more quickly from the cache than if it had to make a request from memory.

When a block is first loaded in the cache it is marked " valid ".

When writing a block in state " valid " its state is changed to " dirty " and a broadcast is sent out to all cache controllers to invalidate their copies.

When the other units are notified of the updated cache, they will turn off the valid bit for their cache of that variable.

When invalidating an address marked as dirty ( i. e. one cache would have a dirty address and the other cache is writing ) then the cache will ignore that request.

When used in cache mode the programmer could configure it as a data or instruction cache, or both, and the internal memory controller then used it to reduce access to ( slower ) external memory.

When performing a reverse lookup, the DNS client converts the address into these formats, and then queries the name for a PTR record following the delegation chain as for any DNS query.

When it receives a request from a client, the DHCP server determines the network to which the DHCP client is connected, and then allocates an IP address or prefix that is appropriate for the client, and sends configuration information appropriate for that client.

When a DHCP-configured client ( a computer or any other network-aware device ) connects to a network, the DHCP client sends a broadcast query requesting necessary information to a DHCP server.

When a DHCP server receives an IP lease request from a client, it reserves an IP address for the client and extends an IP lease offer by sending a DHCPOFFER message to the client.

When other DHCP servers receive this message, they withdraw any offers that they might have made to the client and return the offered address to the pool of available addresses.

When the DHCP server receives the DHCPREQUEST message from the client, the configuration process enters its final phase.

When the client doesn't show up, K. explores the cathedral which is empty except for an old woman and a church official.

When the user wants to do a search, the client sends the request to each actively connected node.

When an LDAP session is created, that is, when an LDAP client connects to the server, the authentication state of the session

When viewing a message with a non-English email client, the header names are usually translated by the client.

When the client exits the session, the mail marked for deletion is removed from the maildrop.

When retrieving new messages, an IMAP client requests the UIDs greater than the highest UID among all previously retrieved messages, whereas a POP client must fetch the entire UIDL map.

: When sent from client to server, ANNOUNCE posts the description of a presentation or media object identified by the request URL to a server.

When sent from server to client, ANNOUNCE updates the session description in real-time.

When the server serves data in a commonly used manner, for example according to the HTTP or FTP protocols, users may have their choice of a number of client programs ( most modern web browsers can request and receive data using both of those protocols ).

When designing using dynamic web-based scripting technics, like classic ASP or PHP, developers must have a keen understanding of the logical, temporal, and physical separation between the client and the server.

When the system is idle, the CPU clocks itself down via lower bus multiplier and selects a lower voltage.

When a program demands more computational resources, the CPU quickly ( there is some latency ) returns to an intermediate or maximum speed with appropriate voltage to meet the demand.

When the PC starts up, the first job for the BIOS is the power-on self-test, which initializes and identifies system devices such as the CPU, RAM, video display card, keyboard and mouse, hard disk drive, optical disc drive and other hardware.

When the computer ran a program that needed access to a peripheral, the Central processing unit ( CPU ) would have to stop executing program instructions while the peripheral processed the data.

When the read is over, the CPU can be interrupted and presented with the read.

When a task switch occurs the CPU can automatically load the new state from the TSS.

When Compaq introduced the first PC based on Intel's new 80386 microprocessor, the Compaq Deskpro 386, in 1986, it marked the first CPU change to the PC platform that was not initiated by IBM.

When a new symbol has been entered, the device typically sends an interrupt to alert the CPU to read it.

When the keyboard processor detects that a key has changed state, it sends a signal to the CPU indicating the scan code of the key and its new state.

When either writing through or directly to physical device registers, this may, but not necessarily, cause a real interrupt to occur at the device's central processor unit ( CPU ), if it has one.

When reading from memory, data addressed by MAR is fed into the MDR ( memory data register ) and then used by the CPU.

When writing to memory, the CPU writes data from MDR to the memory location whose address is stored in MAR.

When there is a write instruction, the data to be written is placed into the MDR from another CPU register, which then puts the data into memory.

When a CPU is executing a program that calls for a floating-point operation, there are three ways to carry it out:

When a CPU is executing a program that calls for a floating-point operation not directly supported by the hardware, the CPU uses a series of simpler floating-point operations.

When you reach a CPU bottleneck, the choices then are either improve the code or add more CPU.

When shared between threads, however, even simple data structures become prone to race hazards if they require more than one CPU instruction to update: two threads may end up attempting to update the data structure at the same time and find it unexpectedly changing underfoot.

** When Epsilon III was discovered to be harboring a gigantic machine in the two part episode " A Voice in the Wilderness ," it is discovered that a living being named Varn had integrated himself with the machine to act as a CPU for the machine.

When originally developed, for the Intel i860, the use of integer math made sense ( both 2D and 3D calculations required it ), but as graphics cards that did much of this became common, integer SIMD in the CPU became somewhat redundant for graphical applications.

When the transfer is complete, the device interrupts the CPU.

When a TOE is used rather than an HBA, the host processor still has to perform the processing of the iSCSI protocol layer itself, but the CPU overhead for that task is low.

* When compared to running on DB2 9, depending on the workload, customers may experience reduced CPU utilization