* L2-Cache: 256 kB, fullspeed

The exception is later Slot 1 CPUs with the Coppermine core which have the L2-Cache embedded into the die.

* Amiga 501 with 512 kB RAM and real-time clock.

The initial Athlon ( Slot A, later called Athlon Classic ) used 512 kB of level 2 cache separate from the CPU, on the processor cartridge board, running at 50 % to 33 % of core speed.

Similar to the Pentium II and the Katmai-based Pentium III, the Athlon Classic contained 512 kB of L2 cache.

Just as Intel had done when they replaced the old Katmai-based Pentium III with the much faster Coppermine-based Pentium III, AMD replaced the 512 kB external reduced-speed cache of the Athlon Classic with 256 kB of on-chip, full-speed exclusive cache.

Based on a J11 CPU equipped with 512 kB of RAM, 64 kB of ROM, and parallel and serial interfaces.

Based on a J11 CPU equipped with 512 kB RAM, 64 kB ROM and parallel and serial interfaces.

A large system might have as little as 256 kB of main storage, but 512 kB, 768 kB or 1024 kB was more common.

The RL and RL / HD featured a 8086 processor, 512 kB of RAM ( expandable to 768 kB to provide 128 kB for video ), smaller keyboard and mouse ports ( which were similar to the PS / 2's ports but not directly compatible ), a bidirectional parallel port instead of the edge-connector ports, and the SL's enhanced graphics and sound.

The RLX offered 512 kB of memory preinstalled, which could be expanded to 1 MB.

To support this, the LaserWriter featured a Motorola 68000 CPU running at 12 MHz, 512 kB of workspace RAM, and a 1 MB frame buffer.

MCS-51 based microcontrollers typically include one or two UARTs, two or three timers, 128 or 256 bytes of internal data RAM ( 16 bytes of which are bit-addressable ), up to 128 bytes of I / O, 512 bytes to 64 kB of internal program memory, and sometimes a quantity of extended data RAM ( ERAM ) located in the external data space.

The Alto had a bit-slice arithmetic logic unit ( ALU ) based on the Texas Instruments ' 74181 chip, a ROM control store with a writable control store extension and had 128 ( expandable to 512 ) kB of main memory organized in 16-bit words.

) These bytes are used to address bytes within the 32 kbit ( 4 kB ) supported by that EEPROM ; the same two byte addressing is also used by larger EEPROMs, such as 24c512 ones storing 512 kbits ( 64 kB ).

Products based on the 3rd generation XScale have up to 512 kB unified L2 cache.

Boards typically included four CPUs and anywhere from 512 kB to 4 MB of SRAM.

All node components were embedded on one chip, with the exception of 512 MB external DRAM.

* L2 cache: 512 KiB external chip on CPU module clocked at CPU-speed

The 750 had support for an optional 256, 512 or 1024 KB external unified L2 cache.

The only changes made were that 512 KB became standard and an external printer connector was added.

** proprietary " Tube " interface for internal or external second CPU ( in the Master 512 model, an 80186 was used ; other options included a 3 MHz extra 6502, a Zilog Z80 for e. g. CP / M, an NS32016, an ARM1, and others )

Single and a few dual SuperSPARC modules with 1 MB external cache were also sold ; they were independently clocked, and ran at a higher rate than the MBus, most commonly 40. 3 MHz or 50 MHz ( uniprocessor Models 41 and 51 ; multiprocessor Models 412, 512 and 514 ).

The machine had either 1K, 4K or 16K memory chips, and typical machines had between 128 to 512 KiB memory.

The design of the memory control logic in R10000 machines supported up to 1 GB RAM, but the thermal output of older generation of DRAM chips necessitated the 512 MB limit.

The Pentium II Xeon, which was aimed at multiprocessor workstations and servers, was largely similar to the later Pentium IIs, being based on the same P6 Deschutes core, aside from a wider choice of L2 cache ranging from 512 to 2048 KB < ref > In the context to semiconductor memory such as cache, KB refers to 2 < sup > 10 </ sup > bytes </ ref > and a full-speed off-die L2 cache ( the Pentium 2 used cheaper 3rd party SRAM chips, running at 50 % of CPU speed, to reduce cost ).

Yaffs1 is the first version of this file system and works on NAND chips that have 512 byte pages + 16 byte spare ( OOB ; Out-Of-Band ) areas.

A slightly larger count ( but still better than split radix for N ≥ 256 ) was shown to be provably optimal for N ≤ 512 under additional restrictions on the possible algorithms ( split-radix-like flowgraphs with unit-modulus multiplicative factors ), by reduction to a Satisfiability Modulo Theories problem solvable by brute force ( Haynal & Haynal, 2011 ).

* Tiles on screen: 512 ( 360 ~ 399 visible, the rest are drawn off screen as a scrolling buffer )

Wireless internet is portable: users can connect nearly anywhere through a receiver ( connected to the client via USB or Ethernet ) and it provides download rates between 512 kbit / s and 1 Mbit / s depending on the chosen plan.

Sector sizes were set as powers of two ( 256 bytes, 512 bytes and so on ) for convenience in processing.

Several public-key cryptography algorithms, such as RSA and the Diffie – Hellman key exchange, are based on large prime numbers ( for example 512 bit primes are frequently used for RSA and 1024 bit primes are typical for Diffie – Hellman .).

Memory and hard drive defaults were increased to 512 MB and 5400 rpm, respectively, with a new storage maximum of 100 GB on the 17-inch model.

* Number of simultaneous colors on screen: 64 out of 512

In contrast to Nortel's DMS-100 which uses individual line cards with a codec, most lines are on two-stage analog space-division concentrators or Line Units, which connect as many as 512 lines, as needed, to the 8 Channel cards that each contain 8 codecs, and to high-level service circuits for ringing and testing.

Year 512 ( DXII ) was a leap year starting on Sunday ( link will display the full calendar ) of the Julian calendar.

Amstrad's final ( and ill-fated ) attempts to exploit the Sinclair brand were based on the company's own PCs ; a compact desktop PC derived from the PPC 512, branded as the Sinclair PC200, and the PC1512 rebadged as the Sinclair PC500.

Union of Lublin of 1569, oil on canvas by Jan Matejko, 1869, 298 × 512 cm, National Museum in Warsaw

The PlayStation 3 game Race Driver: Grid uses 224 simultaneous streams of ATRAC3 compressed audio, with between one and eight channels per stream at sample rates between 24 and 48 kHz, each filtered using 512 frequency bands of adaptive equalisation, routed via six reverb units running on the same SPU co-processor ( one of eight on the PS3's Cell chip ), alongside 7. 1 channel hybrid third-order Ambisonic mixing.

* Caroline Alexander, The Bounty: The True Story of the Mutiny on the Bounty, Viking Penguin, 2003, hardcover, 512 pages, ISBN 0-670-03133-X

Following negative reaction to news surrounding the United States debt ceiling crisis, the Dow closed in correction territory at the 11, 383. 68 level, after a 512. 76 point drop on August 4, 2011.

Users of the PageMaker-LaserWriter-Macintosh 512K system endured frequent software crashes, cramped display on the Mac's tiny 512 x 342 1-bit monochrome screen, the inability to control letter spacing, kerning ( the addition or removal of space between individual characters in a piece of typeset text to improve its appearance or alter its fit ) and other typographic features, and discrepancies between the screen display and printed output.

For each of the 512 possible patterns, the rule table would state whether the center cell will be black or white on the next time interval.

Because of the lack of duplication between caches, Duron can be said to have 192 KB cache on board, whereas an inclusive chip such as Athlon Slot-A, with 512 KB L2, would only have, in practice, 512 KB total ( 640K-128K ).

In fiscal year 2008, the town of Chester spent 1. 04 % ($ 28, 512 ) of its budget on its public library — some $ 22 per person.