* Intel Pentium III, Pentium 4, and Celeron

This trend culminated in large, power-hungry CPUs such as the Intel Pentium 4.

It concluded that complexity of the development was equal to that of a Pentium 4, and promoted a design based on cellular automata.

# Later, more powerful processors, such as Intel P6, AMD K6, AMD K7, and Pentium 4, employed similar dynamic buffering and scheduling principles and implemented loosely coupled superscalar ( and speculative ) execution of micro-operation sequences generated from several parallel x86 decoding stages.

A NASA study recently placed the complexity of a clanking replicator at approximately that of Intel's Pentium 4 CPU.

* NASA Institute for Advance Concepts study by General Dynamics-concluded that complexity of the development was equal to that of a Pentium 4, and promoted a design based on cellular automata.

Introduced in 2004 along with the Prescott revision of the Pentium 4 processor, SSE3 added specific memory and thread-handling instructions to boost the performance of Intel's HyperThreading technology.

Physical Address Extension or PAE was first added in the Intel Pentium Pro, to allow an additional 4 bits of physical addressing in 32-bit protected mode.

In the late 1990s, the idea of executing instructions from multiple threads simultaneously, known as simultaneous multithreading, had reached desktops with Intel's Pentium 4 processor, under the name hyper threading.

Ertl's most recent tests show that direct threading is the fastest threading model on Xeon, Opteron, and Athlon processors ; indirect threading is the fastest threading model on Pentium M processors ; and subroutine threading is the fastest threading model on Pentium 4, Pentium III, and PPC processors.

AMD even ended up playing a significant role in directing the evolution of the x86 platform when its Athlon line of processors continued to develop the classic x86 architecture as Intel deviated with its " Netburst " architecture for the Pentium 4 CPUs and the IA-64 architecture for the Itanium set of server CPUs.

SSE2, introduced with the Pentium 4, further extended the x86 SIMD instruction set with integer ( 8 / 16 / 32 bit ) and double-precision floating-point data support for the XMM register file.

* SSE2, introduced with the Pentium 4, is a major enhancement to SSE.

For this and later releases the SSE-optimized build uses SSE2 and requires a Pentium 4 or later, or AMD Athlon 64 or later.

As recently as the end of 2010, GPL will run flawlessly at 36 frame / s ( its native frame rate ) on the most common hardware such as Pentium 4, Dual core series.

Hyper-threading ( officially Hyper-Threading Technology or HT Technology, abbreviated HTT or HT ) is Intel's term for its simultaneous multithreading implementation first appearing in February 2002 on its Xeon server processors and in November 2002 on its Pentium 4 desktop CPUs.

Intel Pentium 4 processor that incorporates Hyper-Threading Technology

It appeared on the 3. 06 GHz Northwood-based Pentium 4 in the same year, and then appeared in every Pentium 4 HT, Pentium 4 Extreme Edition and Pentium Extreme Edition processor.

This means that at 100 MHz, the Athlon front side bus actually transfers at a rate similar to a 200 MHz single data rate bus ( referred to as 200 MT / s ), which was superior to the method used on Intel's Pentium III ( with SDR bus speeds of 100 MHz and 133 MHz ).

This cache was double the size of K6's already large 2 × 32 kB cache, and quadruple the size of Pentium II and III's 2 × 16 kB L1 cache.

There was a shortage of Pentium III parts.

A PR rating was also necessary because the 6x86 could not clock as high as P5 Pentium and maintain equivalent manufacturing yields, so it was critical to establish the slower clock speeds as equal in the minds of the consumer.

However, it was still considerably slower than the new and completely redesigned P5 Pentium and P6 Pentium Pro-Pentium III FPUs.

The superscalar complexity in the case of modern x86 was solved with dynamically issued and buffered micro-operations, i. e. indirect and dynamic superscalar execution ; the Pentium Pro and AMD K5 are early examples of this.

The Intel P5 Pentium generation was a superscalar version of these principles.

The IntelDX3 was intended to make use of a 2. 5 × multiplier ( used by the Socket3 Pentium Overdrive ), using the same die as the IntelDX4.

Emulation to run existing x86 applications and operating systems was particularly poor, with one benchmark in 2001 reporting that it was equivalent at best to a 100 MHz Pentium in this mode ( 1. 1 GHz Pentiums were on the market at that time ).

The main advantage of this particular microprocessor is that it was designed to fit into existing desktop designs for Pentium branded CPUs.

It was marketed as a product which could perform as well as its Intel Pentium II equivalent but at a significantly lower price.

It was also made pin-compatible with Intel's Pentium, enabling it to be used in the widely available " Socket 7 "- based motherboards.

With the buyout of NexGen, AMD was able to come back into the game with a processor that could perform competitively with Intel's Pentium II.

Against the Pentium, the 68060 could perform better on mixed code, Pentium's decoder could not issue an FP instruction every opportunity and hence the FPU was not superscalar as the ALUs were.

Later, release 3. 0 leveraged the enhancements of newer Intel 486 and Intel Pentium processors — the Virtual Interrupt Flag ( VIF ), which was part of the Virtual Mode Extensions ( VME )— to solve this problem.

The Pentium FDIV bug was a bug in the Intel P5 Pentium floating point unit ( FPU ).

Nicely noticed some inconsistencies in the calculations on June 13, 1994 shortly after adding a Pentium system to his group of computers, but was unable to eliminate other factors ( such as programming errors, motherboard chipsets, etc.

According to Nicely, his contact person at Intel later admitted that Intel had been aware of the problem since May 1994, when the flaw was discovered during testing of the FPU for its new P6 core, first used in the Pentium Pro.

This flaw in the Pentium FPU was quickly verified by other people around the Internet, and became known as the Pentium FDIV bug ( FDIV is the x86 assembly language mnemonic for floating-point division ).

The 80486 and P5 Pentium line of processors were descendants of the 80386 design.

Companies like IBM ( whose IBM 5x86C microprocessor competed at that time with the Intel Pentium line ) joined the condemnation.

The Pentium MMX line was introduced on 22 October 1996.

MMX is a single instruction, multiple data ( SIMD ) instruction set designed by Intel, introduced in 1996 with their P5-based Pentium line of microprocessors, designated as " Pentium with MMX Technology ".

During the Katmai project Intel sought to distinguish it from their earlier product line, particularly their flagship Pentium II.

The fourth generation competed with the P5 Pentium line, but it was not nearly as widely used as its predecessors, since much of the old 68000 marketplace was either defunct or nearly so ( as was the case with Atari and NeXT ), or converting to newer architectures ( PowerPC for the Macintosh and Amiga, SPARC for Sun, and MIPS for SGI ).

The complaint charged that Intel had infringed and was infringing Transmeta's patents by making and selling a variety of microprocessor products, including at least Intel's Pentium III, Pentium 4, Pentium M, Core and Core 2 product line.

The outcome of these development efforts was the Intel Core processor line, and later the Intel Core 2 line, providing and building on the benefits of Pentium M and offering Intel's first native dual core products for desktops and laptops.

This transition marks the end of the NetBurst line of CPU development from Intel that started back with the original Pentium 4.

Dell's Inspiron computer product line started as a range of laptop computers targeted at the entry-level, budget, a Mobile Celeron or Mobile Pentium II processor with SDRAM, and had a high starting price of $ 2, 799.

However, the K6-III also competed against the Pentium III " Katmai " line, released just days later on February 26.

The microprocessor was never released, since the Alpha line of microprocessors was discontinued shortly before HP acquired Compaq which had in turn acquired DEC. Dean Tullsen's work was also used to develop the Hyper-threading ( Hyper-threading technology or HTT ) versions of the Intel Pentium 4 microprocessors, such as the " Northwood " and " Prescott ".

The dual-bus architecture was used in a number of designs, including the IBM and Freescale ( formerly the semiconductor division of Motorola ) PowerPC processors ( certain PowerPC 604 models, the PowerPC 7xx family, and the Freescale 7xxx line ), as well as the Intel Pentium II processor,

* In computing, Yonah is a code name for a processor in Intel's Pentium M line, after Banias and Dothan, branded Intel Core.

The line is notable in that units were offered with either an Alpha AXP or Intel Pentium processor as the CPU, and most hardware other than the backplane and CPU were interchangeable.

The Rise mP6 was a superpipelined and superscalar microprocessor designed by Rise Technology to compete with the Intel Pentium line.

It was succeeded by the NetBurst microarchitecture in 2000, but eventually revived in the Pentium M line of microprocessors.