" SBCL runs on the platforms CMUCL does, except HP / UX ; in addition, it runs on Linux for AMD64, PowerPC, SPARC, MIPS, Windows x86 and has experimental support for running on Windows AMD64.

By porting to Android, MIPS processors power smartphones and tablets running on the operating system.

MIPS Technologies has a strong customer licensee base in home electronics and portable media players ; 75 percent of Blu-ray Disc players are running on MIPS Technologies processors.

* Aug, 2012: MIPS Technologies ports Google's Android 4. 1, " Jelly Bean ". With Indian company Karbonn_Mobiles announces world's second tablet running Android 4. 1.

) This was chosen because the 11 / 780 was roughly equivalent in performance to an IBM System / 370 model 158-3, which was commonly accepted in the computing industry as running at 1 MIPS.

The Data General minicomputers were optionally replaced with an in-house 16-bit design running at 80 MIPS.

A relatively fast dual processor X86 machine running Hercules is capable of sustaining about 50 to 60 MIPS for code that utilizes both processors in a realistic environment, with sustained rates rising to a reported 300 MIPS on leading-edge ( early 2009 ) PC-class systems.

Hercules can produce peaks of over 1200 MIPS when running in a tight loop, such as in a synthetic instruction benchmark or with other small, compute-intensive programs.

Using a RISC design with a 32-bit CPU, at its launch in June 1987, the Archimedes was stated as running at 4 MIPS, with a claim of 18 MIPS during tests.

In 1993, NewTek released the Video Toaster Screamer, a parallel extension to the Toaster, with four motherboards each with a MIPS R4400 CPU running at and of RAM.

For example, an IBM PC with an Intel 80486 CPU running at 50 MHz will be about twice as fast ( internally only ) as one with the same CPU and memory running at 25 MHz, while the same will not be true for MIPS R4000 running at the same clock rate as the two are different processors that implement different architectures and microarchitectures.

Many of these home consumer devices are built around ARM, PowerPC or MIPS processors running an embedded Linux operating system.

A MIPS simulator executes the code for any user programs running on top of the Nachos operating system.

Communications between the MIPS core, the two VPUs, GIF, memory controller and other units is handled by a 128-bit wide internal data bus running at half the clock frequency of the Emotion Engine.

The other project took place only a short drive away at Stanford University under their MIPS effort starting in 1981 and running until 1984.

The MIPS Magnum R4000 PC-50 has a MIPS R4000PC processor with only 16 kB L1 cache ( but no L2 cache ), running at an external clock rate of 50 MHz ( which was internally doubled in the microprocessor to 100 MHz ).

The MIPS Magnum 3000 used a MIPS R3000 processor and a custom, proprietary motherboard which incorporated the TURBOchannel bus ( it is noted that DEC also manufactured the DECstation line of workstations running Ultrix, which also used MIPS processors and the TURBOchannel bus ).

The 6 MHz model operated at 0. 9 MIPS, the 10 MHz model at 1. 5 MIPS, and the 12 MHz model at 2. 66 MIPS.

Meanwhile, the mov reg, reg and ALU reg, reg instructions taking two and three cycles respectively yielded an absolute peak performance of between 1 / 3 and 1 / 2 MIPS per MHz, that is, somewhere in the range 3 – 5 MIPS at 10 MHz.

A 33 MHz 80386 was reportedly measured to operate at about 11. 4 MIPS.

Each KSR1 processor was a custom 64-bit reduced instruction set computing ( RISC ) CPU clocked at 20 MHz and capable of peak output of 20 million instructions per second ( MIPS ) and 40 million floating-point operations per second ( MFLOPS ).

In 1981, a team led by John L. Hennessy at Stanford University started work on what would become the first MIPS processor.

The design was so important to SGI, at the time one of MIPS ' few major customers, that SGI bought the company outright in 1992 in order to guarantee the design would not be lost.

MIPS V is the fifth version of the architecture, announced on 21 October 1996 at the Microprocessor Forum 1996.

The R4000 series, released in 1991, extended the MIPS instruction set to a full 64-bit architecture, moved the FPU onto the main die to create a single-chip microprocessor, and operated at a radically high internal clock speed ( it was introduced at 100 MHz ).

Prior to taking over at MIPS, Vij was an executive at Cavium Networks, Xilinx and Altera.

If the August 14th, 2008 EDN article was accurate about MIPS having over 500 employees at the time, then MIPS reduced their total workforce by 70 % between 2008 and 2010.

* January, 2011: MIPS introduces the first Android-MIPS based Set top box at CES

It was extended to 33 MHz, 5. 4 MIPS for the DragonBall VZ ( MC68VZ328 ) model, and 66 MHz, 10. 8 MIPS for the DragonBall Super VZ ( MC68SZ328 ).

The WebTV set-top box had very limited processing and memory resources ( just a 112 MHz MIPS CPU, 2 megabytes of RAM, 2 megabytes of ROM, 1 megabyte of Flash memory ) and the device relied upon a connection through a 33. 6 kbit / s dialup modem to connect to the WebTV Service, where powerful servers provide back-end support to the WebTV set-top boxes to support a full Web-browsing and email experience for the subscribers.

The computer has a maximum clock rate of 33 MHz and a processing speed of about 35 MIPS.

The first versions released ran at 33 MHz, and Intel promoted the chip as capable of 66 MIPS.

The second subseries, released in 1977-1978, included the models 1015, 1025, 1035, 1045, 1055 and 1060, analogous to System / 370 and operated at 33 kIPS-1. 050 MIPS.

The MIPS Magnum 3000 has a 25 or 33 MHz MIPS R3000A microprocessor.

* Processor: ARM 610 processor at 33 MHz ; approx 28. 7 MIPS.

* Main CPU: MIPS R3000A 32-bit RISC processor @ 33. 8688 MHz, Operating performance-30 MIPS, Instruction Cache-4KB

Two notable examples of this are the ARM compliant AMULET and the MIPS R3000 compatible MiniMIPS.

The performance of the memory hierarchy also greatly affects processor performance, an issue barely considered in MIPS calculations.

The processor is capable of speeds of up to 16. 58 MHz and can run up to 2. 7 MIPS ( million instructions per second ), for the base 68328 and DragonBall EZ ( MC68EZ328 ) model.

Dhrystone tries to represent the result more meaningfully than MIPS ( million instructions per second ) because instruction count comparisons between different instruction sets ( e. g. RISC vs. CISC ) can confound simple comparisons.

However, development of the workstation was well ahead of the PRISM, and the engineers proposed that they release the machines using the MIPS R2000 processor instead, moving its release date up considerably.

EISA was also available on some non-IBM compatible machines such as the AlphaServer, HP 9000-D, SGI Indigo2 and MIPS Magnum.

GDB target processors ( as of 2003 ) include: Alpha, ARM, AVR, H8 / 300, System / 370, System 390, X86 and its 64-bit extension X86-64, IA-64 " Itanium ", Motorola 68000, MIPS, PA-RISC, PowerPC, SuperH, SPARC, and VAX.

Earlier versions also ran on the i860, Alpha, MIPS, Fairchild Clipper, and PowerPC architectures.

IRIX is a computer operating system developed by Silicon Graphics, Inc. ( SGI ) to run natively on their MIPS architecture workstations and servers.

In 1994, IRIX 6. 0 added support for the 64-bit MIPS R8000 processor, but was otherwise similar to IRIX 5. 2.

Later 6. x releases supported other members of the MIPS processor family in 64-bit mode.