The first ( retroactively ) RISC-labeled processor ( IBM 801-IBMs Watson Research Center, mid-1970s ) was a tightly pipelined simple machine originally intended to be used as an internal microcode kernel, or engine, in CISC designs, but also became the processor that introduced the RISC idea to a somewhat larger public.

After the advent of RISC, this philosophy became retroactively known as complex instruction set computing, or CISC.

The term " reduced " in that phrase was intended to describe the fact that the amount of work any single instruction accomplishes is reduced — at most a single data memory cycle — compared to the " complex instructions " of CISC CPUs that may require dozens of data memory cycles in order to execute a single instruction.

* Fast Instruction Set Computer, a term used in computer science describing a CPU where the notion of CISC and RISC have become deprecated.

The PDP-11 introduced a more contemporary model of general registers, numbered R0-R7 or more, adopted by most later CISC and RISC machines.

Key CPU architectural innovations include index register, cache, virtual memory, instruction pipelining, superscalar, CISC, RISC, virtual machine, emulators, microprogram, and stack.

Internal microcode execution in CISC processors, on the other hand, could be more or less pipelined depending on the particular design, and therefore more or less akin to the basic structure of RISC processors.

Due to inherently compact and semantically rich instructions, the average amount of work performed per machine code unit ( i. e. per byte or bit ) is higher for a CISC than a RISC processor, which may give it a significant advantage in a modern cache based implementation.

The terms CISC and RISC have become less meaningful with the continued evolution of both CISC and RISC designs and implementations.

Compared to a small 8-bit CISC processor, a RISC floating-point instruction is complex.

CISC does not even need to have complex addressing modes ; 32 or 64-bit RISC processors may well have more complex addressing modes than small 8-bit CISC processors.

For instance, the PDP-8, having only 8 fixed-length instructions and no microcode at all, is a CISC because of how the instructions work, PowerPC, which has over 230 instructions ( more than some VAXes ) and complex internals like register renaming and a reorder buffer is a RISC, while Minimal CISC has 8 instructions, but is clearly a CISC because it combines memory access and computation in the same instructions.

Some of the problems and contradictions in this terminology will perhaps disappear as more systematic terms, such as ( non ) load / store, becomes more popular and eventually replaces the imprecise and slightly counter-intuitive RISC / CISC terms.

* RISC vs. CISC comparison

Dhrystone tries to represent the result more meaningfully than MIPS ( million instructions per second ) because instruction count comparisons between different instruction sets ( e. g. RISC vs. CISC ) can confound simple comparisons.

For example, the same high-level task may require many more instructions on a RISC machine, but might execute faster than a single CISC instruction.

Alpha, originally known as Alpha AXP, is a 64-bit reduced instruction set computer ( RISC ) instruction set architecture ( ISA ) developed by Digital Equipment Corporation ( DEC ), designed to replace the 32-bit VAX complex instruction set computer ( CISC ) ISA and its implementations.

When first released in 2001, Itanium's performance, compared to better-established RISC and CISC processors, was disappointing.

During development, Intel, HP, and industry analysts predicted that IA-64 would dominate in servers, workstations, and high-end desktops, and eventually supplant RISC and complex instruction set computer ( CISC ) architectures for all general-purpose applications.

By the time Itanium was released in June 2001, its performance was not superior to competing RISC and CISC processors.

IA-32 ( Intel Architecture, 32-bit ), also known as x86-32, i386 or x86, is the CISC instruction-set architecture of Intel's most commercially successful microprocessors, and was first implemented in the Intel 80386 as a 32-bit extension of x86 architecture.

The opposing architecture is known as complex instruction set computing, i. e. CISC.

The AS / 400 was originally based on a custom IBM CISC CPU which used a CPU architecture known as Internal MicroProgrammed Interface ( IMPI ) and an instruction set similar to the IBM 370.

This was partly inspired by the difficulty Fisher observed at Yale of compiling for architectures like Floating Point Systems ' FPS164, which had a complex instruction set architecture ( CISC ) that separated instruction initiation from the instructions that saved the result, requiring very complicated scheduling algorithms.

* DEC achieved similar success with its translation tools to help users migrate from the CISC VAX architecture to the Alpha RISC architecture.

Based on his PhD research, his pioneering architecture of technology-independent machine interfaces ( TIMI ) and single-level stores has appeared in these eight generations of IBM hardware: System / 38 in 1978, the CISC AS / 400 in 1988, the RISC AS / 400 in 1995, the web server AS / 400e in 1999 ( supporting HTTP and TCP / IP ), the eServer iSeries, the System i5, the System i, and IBM Power Systems running IBM i ( April, 2008 ).

It runs the HP 3000 family of computers, which originally used HP custom 16 bit stack architecture CISC CPUs and were later migrated to PA-RISC where the operating system was called MPE / XL.

Different instructions may take different amounts of time ( e. g., CISC architecture ).

The brainchild of James Billmaier, Mario Pagliaro, Armando Stettner and Joseph DiNucci, the systems family was to also employ a truly RISC-based architecture when compared to the heavier and very CISC VAX or the then still under development Prism architectures.

Despite being initially written for a single computer architecture, Open64 has proven that it can generate efficient code for CISC, RISC, and VLIW architectures, including MIPS, x86, IA-64, ARM, and others.

The Clipper architecture used a simplified instruction set compared to earlier CISC architectures, but it did incorporate some more complicated instructions than were present in other contemporary RISC processors.

The x86 CISC based CPU architecture which Intel introduced in 1978 was used as the standard for the DOS based IBM PC, and developments of it still continue to dominate the Microsoft Windows market.

Although complex, the transistor count of CISC decoders do not grow exponentially like the total number of transistors per processor ( the majority typically used for caches ).

This proved fairly successful due to the simplicity of the core, which allowed it to be used in a number of applications that would have formerly used much less capable CISC designs of similar gate count and price — the two are strongly related ; the price of a CPU is generally related to the number of gates and the number of external pins.

* RISC vs CISC: CISC instruction sets often have variable instruction lengths, often have a larger number of possible instructions that can be used, and each instruction could take differing amounts of time.

A complex instruction set computer ( CISC, ) is a computer where single instructions can execute several low-level operations ( such as a load from memory, an arithmetic operation, and a memory store ) and / or are capable of multi-step operations or addressing modes within single instructions.

But they are all in the CISC category because they have " load-operate " instructions that load and / or store memory contents within the same instructions that perform the actual calculations.

) However, pipelining at that level was already used in some high performance CISC " supercomputers " in order to reduce the instruction cycle time ( despite the complications of implementing within the limited component count and wiring complexity feasible at the time ).

Due to the reduced complexity of the Classic RISC pipeline, the pipelined core and an instruction cache could be placed on the same size die that would otherwise fit the core alone on a CISC design.

In a more modern context, the complex variable length encoding used by some of the typical CISC architectures makes it complicated, but still feasible, to build a superscalar implementation of a CISC programming model directly ; the in-order superscalar original Pentium and the out-of-order superscalar Cyrix 6x86 are well known examples of this.

One symptom was the poor performance of its largest implementation, but the project was also marred by protracted internal arguments about various technical aspects, including internal IBM debates about the merits of RISC vs. CISC designs.