The first commercial RISC microprocessor design was released either by MIPS Computer Systems, the 32-bit R2000 ( the R1000 was not released ) or by Acorn computers, the 32-bit ARM2 in 1987.

A major aspect of the MIPS design was to fit every sub-phase, including cache-access, of all instructions into one cycle, thereby removing any needs for interlocking, and permitting a single cycle throughput.

The other difference between the MIPS design and the competing Berkeley RISC involved the handling of subroutine calls.

In other ways the MIPS design was very much a typical RISC design.

In 1984 Hennessy was convinced of the future commercial potential of the design, and left Stanford to form MIPS Computer Systems.

The design was so important to SGI, at the time one of MIPS ' few major customers, that SGI bought the company outright in 1992 in order to guarantee the design would not be lost.

Fully half of MIPS ' income today comes from licensing their designs, while much of the rest comes from contract design work on cores that will then be produced by third parties.

One of the first start-ups to design MIPS processors was Quantum Effect Devices ( see next section ).

The MIPS design team that designed the R4300i started the company SandCraft, which designed the R5432 for NEC and later produced the SR71000, one of the first out-of-order execution processors for the embedded market.

The R3000 was the first successful MIPS design in the marketplace, and eventually over one million were made.

The R8000 ( 1994 ) was the first superscalar MIPS design, able to execute two integer or floating point and two memory instructions per cycle.

Modern mainframe design is generally less defined by single-task computational speed ( typically defined as MIPS rate or FLOPS in the case of floating point calculations ), and more by:

MIPS Technologies, Inc. (), formerly MIPS Computer Systems, Inc., is a semiconductor design company that is most widely known for developing the MIPS architecture and a series of RISC CPU chips.

< tt > MMIX </ tt > ( pronounced em-mix ) is a 64-bit RISC architecture designed by Donald Knuth, with significant contributions by John L. Hennessy ( who contributed to the design of the MIPS architecture ) and Richard L. Sites ( who was an architect of the Alpha architecture ).

Development of new MIPS microprocessors stopped, and the existing R12000 design was extended multiple times until 2003 to provide existing customers more time to migrate to Itanium.

When the semiconductor division of DEC was sold to Intel, many engineers from the Palo Alto design group moved to SiByte, a start-up company designing MIPS system-on-a-chip ( SoC ) products for the networking market.

The Austin design group spun off to become Alchemy Semiconductor, another start-up company designing MIPS SoCs for the hand-held market.

The Data General minicomputers were optionally replaced with an in-house 16-bit design running at 80 MIPS.

Using a RISC design with a 32-bit CPU, at its launch in June 1987, the Archimedes was stated as running at 4 MIPS, with a claim of 18 MIPS during tests.

The Sony PlayStation Portable uses two processors based on the MIPS R4000 processor.

* MAME uses dynamic recompilation in its CPU emulators for MIPS, SuperH, PowerPC and even the Voodoo graphics processing units.

Moravec talks in terms of MIPS, not " cps ", which is a non-standard term Kurzweil introduced .</ ref > He uses this figure to predict the necessary hardware will be available sometime between 2015 and 2025, if the current exponential growth in computer power continues.

The codec uses a bit rate of 2. 4 kbit / s, requiring 20 MIPS of processing power, 2 kilobytes of RAM and features a frame size of 22. 5 ms. Additionally, the codec requires a large lookahead of 90 ms.

As an example Infineon uses an AMBA bus for the ADM5120 SoC based on the MIPS architecture.

The Propeller runs at 80 MHz and uses eight processor cores, called COGs, to reach a performance of 160 MIPS.

Programming is introduced through Scheme and functional programming throughout the first semester, in parallel with the computer architecture course ( which uses MIPS assembly ).

The Alchemy microprocessor is a low power processor family that uses MIPS architecture.

In 1994, IRIX 6. 0 added support for the 64-bit MIPS R8000 processor, but was otherwise similar to IRIX 5. 2.

Later 6. x releases supported other members of the MIPS processor family in 64-bit mode.

SGI announced the end of the MIPS / IRIX-based product line in a press release on 6 September 2006.

The 6 MHz model operated at 0. 9 MIPS, the 10 MHz model at 1. 5 MIPS, and the 12 MHz model at 2. 66 MIPS.

On September 6, 2006, SGI announced the end of development for the MIPS / IRIX line and the IRIX operating system.

* Computation – The world's technological capacity to compute information with humanly guided general-purpose computers grew from 3. 0 × 10 < sup > 8 </ sup > MIPS in 1986, to 4. 4 × 10 < sup > 9 </ sup > MIPS in 1993, 2. 9 × 10 < sup > 11 </ sup > MIPS in 2000 to 6. 4 × 10 < sup > 12 </ sup > MIPS in 2007.

The world's technological capacity to compute information with humanly guided general-purpose computers grew from 3. 0 × 10 ^ 8 MIPS in 1986, to 6. 4 x 10 ^ 12 MIPS in 2007, experiencing the fastest growth rate of over 60 % per year during the last two decades.

The WebTV set-top box had very limited processing and memory resources ( just a 112 MHz MIPS CPU, 2 megabytes of RAM, 2 megabytes of ROM, 1 megabyte of Flash memory ) and the device relied upon a connection through a 33. 6 kbit / s dialup modem to connect to the WebTV Service, where powerful servers provide back-end support to the WebTV set-top boxes to support a full Web-browsing and email experience for the subscribers.

It contains 6, 144 MIPS R10000 microprocessors.

* MIPS based core: 2 issue, 2 64-bit fixed point units, 1 floating point unit, 6 stage pipeline

The MIPS architecture provides a specific example for a machine code whose instructions are always 32 bits long.

They are based on a RISC architecture of 8 bits and can reach speeds up to 100 MIPS on the Virtex 4 FPGA's family.

The early MIPS architectures were 32-bit, and later versions were 64-bit.

In 1999 MIPS formalized their licensing system around two basic designs, the 32-bit MIPS32 ( based on MIPS II with some additional features from MIPS III, MIPS IV, and MIPS V ) and the 64-bit MIPS64 ( based on MIPS V ).

MIPS V added a new data type, the pair-single ( PS ), which consisted of two single-precision ( 32-bit ) floating-point numbers stored in the existing 64-bit floating-point registers.

Other licensees include Broadcom, which has developed MIPS-based CPUs for over a decade, Microchip Technology, which leverages MIPS processors for its 32-bit PIC32 microcontrollers, and Mobileye, whose EyeQ2 and EyeQ3 are based on cores licensed from MIPS.

* Processor: Two SH2 32-bit RISC processors with a clock speed of 23. 011 MHz, approx 20 MIPS each

RISC processors using 32-bit instructions are usually 3-operand machines, such as processors implementing the Power Architecture, the SPARC architecture, the MIPS architecture, the ARM architecture, and the AVR32 architecture.

Prominent 32-bit instruction set architectures include the IBM System / 360 and its 32-bit successors, the DEC VAX, the Motorola 68k, the ARM architecture, the Intel IA-32, and the 32-bit versions of the SPARC, MIPS, PowerPC, and PA-RISC architectures.

The combination of a compact 16-bit instruction encoding with a more powerful 32-bit instruction encoding is not unique to SH-5 ; ARM processors have a 16-bit Thumb mode, and MIPS processors have a MIPS-16 mode.

Each module delivered 2 MIPS, 500 kiloFLOPS ( 32-bit single precision ), or 300 kiloFLOPS ( 64-bit double precision ), and ran the Vertex operating system.

Most high performance 32-bit and 64-bit processors ( some notable exceptions are most ARM and 32-bit MIPS CPUs ) have integrated floating point hardware, which is often, but not always, based on 64-bit units of data.

The DLX has a simple 32-bit load / store architecture, somewhat unlike the modern MIPS CPU.