The POWER1 is a multi-chip CPU developed and fabricated by IBM that implemented the POWER instruction set architecture ( ISA ).

An indirect derivative of the POWER1 is the PowerPC 601, a feature-reduced variant of the RSC intended for consumer applications.

The POWER1 is notable as it represented a number firsts for IBM and computing in general.

The POWER1 is a 32-bit two-way superscalar CPU.

Although the POWER1 is a 32-bit CPU with a 32-bit physical address, its virtual address is 52 bits long.

The POWER1 is a big-endian CPU that uses a Harvard style cache hierarchy with separate instruction and data caches.

The POWER1 is a multi-chip CPU built from separate chips that are connected to each other by buses.

The chips that make up the POWER1 is fabricated in a 1. 0 µm CMOS process with three layers of interconnect.

The total number of transistors featured by the POWER1, assuming that it is a RIOS-1 configuration, is 6. 9 million, with 2. 04 million used for logic and 4. 86 million used for memory.

In most processors, a multiply and an add, which is common in technical and scientific floating-point code, cannot be executed in one cycle, as in the POWER1.

Compared to the POWER1, the RSC memory data bus is narrower and uses industry standard SIMMs instead of custom memory cards.

These upgraded versions were clocked higher than the original POWER1, made possible by improved semiconductor processes.

In September 1993, the POWER1 and its variants was succeeded by the POWER2 ( known briefly as the " RIOS2 "), an evolution of the POWER1 microarchitecture.

Although the POWER1 was a high-end design, it was not capable of multiprocessing, and as such was disadvantaged, as the only way performance could be improved was by clocking the CPU higher, which was difficult to do with such a large multi-chip design.

IBM used clustering to overcome this disadvantage in POWER1 systems, allowing them to effectively function as if they were multiprocessing systems, a concept proven by the popularity of SP1 supercomputers based on the POWER1.

The POWER1 consists of an instruction-cache unit ( ICU ), a fixed-point unit ( FXU ), a floating point unit ( FPU ), a number of data-cache units ( DCU ), a storage-control unit ( SCU ) and a I / O unit.

* RISC Single Chip-the singe chip version of the POWER1 processor

The RS / 6000 CPU had 2 configurations, called the " RIOS-1 " and " RIOS. 9 " ( or more commonly the " POWER1 " CPU ).

IBM started the POWER2 processor effort as a successor to the POWER1 two years before the creation of the 1991 Apple / IBM / Motorola alliance in Austin, Texas.

The CPU was the PowerPC, a single-chip version of IBM's POWER1 CPU.

In 1990, IBM introduced the first out-of-order microprocessor, the POWER1, although out-of-order execution was limited to floating point instructions only.

The POWER1 was introduced in 1990, with the introduction of the IBM RS / 6000 POWERserver servers and POWERstation workstations, which featured the POWER1 clocked at 20, 25 or 30 MHz.

The POWER1 + was clocked slightly higher than the original POWER1, at frequencies of 25, 33 and 41 MHz, while the POWER1 ++ took the microarchitecture to its highest frequencies — 25, 33, 41. 6, 45, 50 and 62. 5 MHz.

The direct derivatives of the POWER1 are the RISC Single Chip ( RSC ), feature-reduced single-chip variant for entry-level RS / 6000 systems, and the RAD6000, a radiation-hardened variant of the RSC for space applications.

For computing firsts, the POWER1 would be known for being the first CPU to implement some form of Register renaming and out-of-order execution, a technique that improves the performance of superscalar processors but was previously reserved for mainframes.

The POWER1 was also the origin for the highly successful families of POWER, PowerPC and Power Architecture processors that followed it, measuring in hundreds of different implementations.

The open source GCC compiler removed support for POWER1 ( RIOS ) and POWER2 ( RIOS2 ) in the 4. 5 release.

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