Boundary scan testing requires that all the ICs to be tested use a standard test configuration procedure, the most common one being the Joint Test Action Group ( JTAG ) standard.

Once imported, the developer should be able to transfer the circuit via a Joint Test Action Group ( JTAG ) cable.

Joint Test Action Group ( JTAG ) is the common name for what was later standardized as the IEEE 1149. 1 Standard Test Access Port and Boundary-Scan Architecture.

* JTAG is a standard test interface defined by the Joint Test Action Group and supported on many late-model digital receivers for factory test purposes.

The Joint Test Action Group ( JTAG ) developed a specification for boundary scan testing that was standardized in 1990 as the IEEE Std.

These cells are then connected together to form the external boundary scan shift register ( BSR ), and combined with JTAG TAP ( Test Access Port ) controller support comprising four ( or sometimes more ) additional pins plus control circuitry.

* Debugging: JTAG, ISP, ICSP, BDM Port, BITP, and DP9 ports.

* test access port ( TAP ) in JTAG

* The OMAP2420, which includes a boundary scan TAP, the ARM1136 Debug TAP, an ETB11 trace buffer tap, a C55x DSP, and a tap for an ARM7TDMI-based imaging engine, with the boundary scan TAP (" ICEpick-B ") having the ability to splice TAPs into and out of the JTAG scan chain.

* The i. MX31 processor, which is similar, although its " System JTAG " boundary scan TAP, which is very different from ICEpick, and it includes a TAP for its DMA engine instead of a DSP and imaging engine.

Those processors are both intended for use in wireless handsets such as cell phones, which is part of the reason they include TAP controllers which modify the JTAG scan chain: Debugging low power operation requires accessing chips when they are largely powered off, and thus when not all TAPs are operational.

This debug TAP exposes several standard instructions, and a few specifically designed for hardware-assisted debugging, where a software tool ( the " debugger ") uses JTAG to communicate with a system being debugged:

OnCE includes a JTAG command which makes a TAP enter a special mode where the IR holds OnCE debugging commands for operations such as single stepping, breakpointing, and accessing registers or memory.

Some TAP controllers support scan chains between on-chip logical design blocks, with JTAG instructions which operate on those internal scan chains instead of the BSR.

The " D " represented a JTAG TAP for debugging ; the " I " denoted an ICEBreaker debug module supporting hardware breakpoints and watchpoints, and letting the system be stalled for debugging.

These pins can be configured to function as JTAG or GPIO depending on the setting of a fuse bit, which can be programmed via ISP or HVSP.

Emulating the processor, or direct JTAG access to it, lets the ICE do anything that the processor can do, but under the control of a software developer.

The same JTAG techniques used to debug software running inside a CPU can help debug other digital design blocks inside an FPGA.

For example, custom JTAG instructions can be provided to allow reading registers built from arbitrary sets of signals inside the FPGA, providing visibility for behaviors which are invisible to boundary scan operations.

In the case of FPGAs, volatile memory devices can also be programmed via the JTAG port normally during development work.

By using JTAG to manipulate its internal interface ( to on-chip registers ), the combinational logic can be tested.

A JTAG interface is a special four / five-pin interface added to a chip, designed so that multiple chips on a board can have their JTAG lines daisy-chained together if specific conditions are met, and a test probe need only connect to a single " JTAG port " to have access to all chips on a circuit board.

There are generally some processor-specific JTAG operations which can reset all or part of the chip being debugged.

The JTAG state machine can reset, access an instruction register, or access data selected by the instruction register.

Halting it puts the core into the " Debug Mode ", where the ITR can be used to execute instructions, including using the DCC to transfer data between the debug ( JTAG ) host and the CPU.

They are also decoupled from JTAG so they can be hosted over ARM's two-wire " SWD " interface instead of just the six-wire JTAG interface.

** Almost all FPGAs and CPLDs used today can be programmed via a JTAG port.

A special JTAG card can be used to reflash a corrupt BIOS.

* JTAG can also support field updates and troubleshooting.

Through a JTAG or BDM test port, the probe can debug and control the core state ( such as CPU internal registers ) as well as the system state ( external RAM and flash memory ).

These cells can be programmed via the JTAG scan chain to drive a signal onto a pin and across an individual trace on the board.

EEPROM versions may be in-system programmable ( typically via JTAG ).

JTAG was meant to provide a pins-out view from one IC pad to another so all these faults could be discovered.

Debug support is, for many software developers, the main reason to be interested in JTAG.

There are entire debugging architectures built up using JTAG, such as ARM CoreSight and Nexus ( plus vendor-specific ones that may not be documented except under NDA ) helping move JTAG-centric debugging environments away from early processor-specific designs.

Behind those registers is hardware that is not specified by JTAG, and which has its own states that will be affected by JTAG activities.

Issuing a HALT instruction using JTAG might be dangerous.

Recent ICEs enable a programmer to access the on-chip debug circuit that is integrated into the CPU via JTAG or BDM ( Background Debug Mode ) in order to debug the software of an embedded system.

The controller modules interface with the system " centerplane " via JTAG and control the partitioning of available CPUs, memory and I / O devices into one or more domains, each of which is in effect a distinct computer.

Besides debugging, another application of JTAG is allowing device programmer hardware to transfer data into internal non-volatile device memory ( e. g. CPLDs ).

JTAG programmers are also used to write software and data into flash memory.

Installing firmware into Flash, or SRAM in place of Flash, via JTAG is intermediate between these extremes, as well as in cost of hardware tools.

Faster TCK frequencies are most useful when JTAG is used to transfer lots of data, such as when storing a program executable into flash memory.

The processor itself has extensive JTAG capability, similar to what is found in other CPU cores, and it's integrated into chips with even more extensive capabilities accessed through JTAG.