JTAG is a standard and popular interface ; many CPUs, microcontrollers and other devices are manufactured with JTAG interfaces ( as of 2009 ).

JTAG tool vendors provide various types of stimulus and sophisticated algorithms, not only to detect the failing nets, but also to isolate the faults to specific nets, devices, and pins.

* On-chip debugging ( OCD ) support through JTAG or debugWIRE on most devices

The controller modules interface with the system " centerplane " via JTAG and control the partitioning of available CPUs, memory and I / O devices into one or more domains, each of which is in effect a distinct computer.

In the case of FPGAs, volatile memory devices can also be programmed via the JTAG port normally during development work.

On JTAG devices with SWD capability, the TMS and TCK are used as SWDIO and SWCLK signals, providing for dual-mode programmers.

Typically high-end commercial JTAG testing systems allow the import of design ' netlists ' from CAD / EDA systems plus the BSDL models of boundary scan / JTAG compliant devices to automatically generate test applications.

Boundary scan testing requires that all the ICs to be tested use a standard test configuration procedure, the most common one being the Joint Test Action Group ( JTAG ) standard.

JTAG was meant to provide a pins-out view from one IC pad to another so all these faults could be discovered.

A so-called in-circuit emulator ( or more correctly, " JTAG adapter ") uses JTAG as the transport mechanism to access on-chip debug modules inside the target CPU.

The processor itself has extensive JTAG capability, similar to what is found in other CPU cores, and it's integrated into chips with even more extensive capabilities accessed through JTAG.

( However, trace data is too voluminous to use JTAG as more than a trace control channel.

These cells are then connected together to form the external boundary scan shift register ( BSR ), and combined with JTAG TAP ( Test Access Port ) controller support comprising four ( or sometimes more ) additional pins plus control circuitry.

The JTAG test architecture provides a means to test interconnects between integrated circuits on a board without using physical test probes.

Now, many CPUs use a standard serial test interface, usually JTAG, for this purpose.

* test access port ( TAP ) in JTAG

JTAG was an industry group formed in 1985 to develop a method to test populated circuit boards after manufacture.

By using JTAG to manipulate the chip's external interface ( inputs and outputs to other chips ) it is possible to test for certain faults, caused mainly by manufacturing problems.

A JTAG interface is a special four / five-pin interface added to a chip, designed so that multiple chips on a board can have their JTAG lines daisy-chained together if specific conditions are met, and a test probe need only connect to a single " JTAG port " to have access to all chips on a circuit board.

So at a basic level, using JTAG involves reading and writing instructions and their associated data registers ; and sometimes involves running a number of test cycles.

Through a JTAG or BDM test port, the probe can debug and control the core state ( such as CPU internal registers ) as well as the system state ( external RAM and flash memory ).

* JTAG is a standard test interface defined by the Joint Test Action Group and supported on many late-model digital receivers for factory test purposes.

Operating using a six-wire interface and a personal computer, the JTAG interface was originally intended to provide a means to test and debug embedded hardware and software.

* JTAG access to hardware debug interfaces such as those on ARM architecture processors or using the Nexus command set.

More recently the term also covers JTAG based hardware debuggers which provide equivalent access using on-chip debugging hardware with standard production chips.

Emulating the processor, or direct JTAG access to it, lets the ICE do anything that the processor can do, but under the control of a software developer.

Recent ICEs enable a programmer to access the on-chip debug circuit that is integrated into the CPU via JTAG or BDM ( Background Debug Mode ) in order to debug the software of an embedded system.

This is usually done using data bus access like the CPU would use, and is sometimes actually handled by a CPU, but in other cases memory chips have JTAG interfaces themselves.

The JTAG state machine can reset, access an instruction register, or access data selected by the instruction register.

* Primarily of historical interest: Intel's Pentium processors supported a " probe mode " supporting JTAG access for debuggers.

In the satellite TV world, JTAG is most often used to obtain read-write access to nonvolatile memory within a digital receiver ; initially programs such as Wall and JKeys were used to read box keys from receivers with embedded CAMs but JTAG has since proven its legitimate worth to satellite TV fans as a repair tool to fix receivers where the firmware ( in flash memory ) has been corrupted.

However, neither the IDE nor a debugger were included, so for debugging and JTAG access to the DSPs, users still need to purchase the complete toolchain.

* Debugging: JTAG, ISP, ICSP, BDM Port, BITP, and DP9 ports.

Today JTAG is also widely used for IC debug ports.

* Solder pads for user-supplied connectors: 2 8-bit I / O ports, ISP, USI, JTAG

The board also has ISP and JTAG ports for in-circuit programming and debugging.

* The OMAP2420, which includes a boundary scan TAP, the ARM1136 Debug TAP, an ETB11 trace buffer tap, a C55x DSP, and a tap for an ARM7TDMI-based imaging engine, with the boundary scan TAP (" ICEpick-B ") having the ability to splice TAPs into and out of the JTAG scan chain.

Those processors are both intended for use in wireless handsets such as cell phones, which is part of the reason they include TAP controllers which modify the JTAG scan chain: Debugging low power operation requires accessing chips when they are largely powered off, and thus when not all TAPs are operational.

EEPROM versions may be in-system programmable ( typically via JTAG ).

The 80960Jx ’ s testability features included ONCE ( on-circuit emulation ) mode and boundary scan ( JTAG ).

Besides debugging, another application of JTAG is allowing device programmer hardware to transfer data into internal non-volatile device memory ( e. g. CPLDs ).

When combined with built-in self-test ( BIST ), the JTAG scan chain enables a low overhead, embedded solution to testing an IC for certain static faults ( shorts, opens, and logic errors ).

Some circuits have a serial interface for receiving the programming data ( JTAG interface ).