This debug TAP exposes several standard instructions, and a few specifically designed for hardware-assisted debugging, where a software tool ( the " debugger ") uses JTAG to communicate with a system being debugged:

Many vendors do not publish the protocols used by their JTAG adapter hardware, limiting their customers to the tool chains supported by those vendors.

In the satellite TV world, JTAG is most often used to obtain read-write access to nonvolatile memory within a digital receiver ; initially programs such as Wall and JKeys were used to read box keys from receivers with embedded CAMs but JTAG has since proven its legitimate worth to satellite TV fans as a repair tool to fix receivers where the firmware ( in flash memory ) has been corrupted.

* Wiggler ( JTAG ), a parallel port JTAG tool from the Macraigor Systems LLC.

More recently the term also covers JTAG based hardware debuggers which provide equivalent access using on-chip debugging hardware with standard production chips.

JTAG was meant to provide a pins-out view from one IC pad to another so all these faults could be discovered.

Even though few consumer products provide an explicit JTAG port connector, the connections are often available on the printed circuit board as a remnant from development prototyping and / or production.

* Chip Vendors may provide the tools, usually requiring a JTAG adapter they supply.

Operating using a six-wire interface and a personal computer, the JTAG interface was originally intended to provide a means to test and debug embedded hardware and software.

A JTAG interface is a special four / five-pin interface added to a chip, designed so that multiple chips on a board can have their JTAG lines daisy-chained together if specific conditions are met, and a test probe need only connect to a single " JTAG port " to have access to all chips on a circuit board.

One chip might have a 40 MHz JTAG clock, but only if it's using a 200 MHz clock for non-JTAG operations ; and it might need to use a much slower clock when it's in a low power mode.

Current x86 processors appear to use JTAG only for boundary scan.

* It is also possible to take control of a system by using a hardware debug interface such as JTAG.

Today JTAG is also widely used for IC debug ports.

Sometimes FPGA developers also use JTAG to develop debugging tools.

In the case of FPGAs, volatile memory devices can also be programmed via the JTAG port normally during development work.

JTAG programmers are also used to write software and data into flash memory.

They are also decoupled from JTAG so they can be hosted over ARM's two-wire " SWD " interface instead of just the six-wire JTAG interface.

* JTAG can also support field updates and troubleshooting.

There are also CPU emulators that either replace the CPU or connect via a JTAG port, with the Sage SmartProbe being an example.

The board also has ISP and JTAG ports for in-circuit programming and debugging.

By using JTAG to manipulate the chip's external interface ( inputs and outputs to other chips ) it is possible to test for certain faults, caused mainly by manufacturing problems.

When combined with built-in self-test ( BIST ), the JTAG scan chain enables a low overhead, embedded solution to testing an IC for certain static faults ( shorts, opens, and logic errors ).

JTAG is a standard and popular interface ; many CPUs, microcontrollers and other devices are manufactured with JTAG interfaces ( as of 2009 ).

* On-chip debugging ( OCD ) support through JTAG or debugWIRE on most devices

The controller modules interface with the system " centerplane " via JTAG and control the partitioning of available CPUs, memory and I / O devices into one or more domains, each of which is in effect a distinct computer.

In JTAG, devices expose one or more test access ports ( TAPs ).

On JTAG devices with SWD capability, the TMS and TCK are used as SWDIO and SWCLK signals, providing for dual-mode programmers.

Typically high-end commercial JTAG testing systems allow the import of design ' netlists ' from CAD / EDA systems plus the BSDL models of boundary scan / JTAG compliant devices to automatically generate test applications.

* Microcontrollers with as few as six pins need to use low pin-count substitutes for JTAG, such as BDM, Spy-Bi-Wire, or debugWIRE on the Atmel AVR.

These pins can be configured to function as JTAG or GPIO depending on the setting of a fuse bit, which can be programmed via ISP or HVSP.

In the embedded processor market, essentially all modern processors implement JTAG when they have enough pins.

However, the very smallest chips may not have enough pins to spare ( and thus tend to rely on proprietary single-wire programming interfaces ); if the pin count is over 32, there is probably a JTAG option.

* The PCI bus connector standard contains optional JTAG signals on pins 1-5 ; PCI-Express contains JTAG signals on pins 5-9.

These cells are then connected together to form the external boundary scan shift register ( BSR ), and combined with JTAG TAP ( Test Access Port ) controller support comprising four ( or sometimes more ) additional pins plus control circuitry.

This file is transferred to the FPGA / CPLD via a serial interface ( JTAG ) or to an external memory device like an EEPROM.

Recent microcontrollers are often integrated with on-chip debug circuitry that when accessed by an in-circuit emulator via JTAG, allow debugging of the firmware with a debugger.

* Debugging: JTAG, ISP, ICSP, BDM Port, BITP, and DP9 ports.

* An in-circuit debugger ( ICD ), a hardware device that connects to the microprocessor via a JTAG or Nexus interface.

* JTAG access to hardware debug interfaces such as those on ARM architecture processors or using the Nexus command set.

Processors used in embedded systems typically have extensive JTAG debug support.

Boundary scan testing requires that all the ICs to be tested use a standard test configuration procedure, the most common one being the Joint Test Action Group ( JTAG ) standard.

The JTAG test architecture provides a means to test interconnects between integrated circuits on a board without using physical test probes.

** The JTAG signals ( TMS, TDI, TDO, and TCK ) are multiplexed on GPIOs.

By default, AVRs with JTAG come with the JTAG interface enabled.

Now, many CPUs use a standard serial test interface, usually JTAG, for this purpose.

Very common is boundary scan testing using IEEE 1149. 1 JTAG port.

Emulating the processor, or direct JTAG access to it, lets the ICE do anything that the processor can do, but under the control of a software developer.

For example, it is routine to have a source code level debugger with a graphical windowing interface that communicates through a JTAG adapter (" emulator ") to an embedded target system which has no graphical user interface.

Recent ICEs enable a programmer to access the on-chip debug circuit that is integrated into the CPU via JTAG or BDM ( Background Debug Mode ) in order to debug the software of an embedded system.

The CPU delays were managed through careful tuning of each PCB manufactured in conjunction with the logic technology and incorporated two key technologies known as JTAG and BIST.

Once imported, the developer should be able to transfer the circuit via a Joint Test Action Group ( JTAG ) cable.